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Chip package structure

A chip packaging structure and chip technology, applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of affecting the heat sink, the design freedom of components is small, and the distance along the surface and the space distance cannot be effectively increased, so as to increase the space distance , the effect of increasing the distance along the surface

Active Publication Date: 2011-12-14
CYNTEC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the cooling fins 110 with a special shape can only be produced by using a specially designed mold, therefore, the manufacturing cost of the cooling fins 110 is relatively high
In addition, when designing the components inside the encapsulant 140 (such as the bonding wire 150, the chip 160, the substrate 130, and some leads 120), the position of the aforementioned components should avoid the groove 142, so as to avoid the groove 142 exposing the aforementioned components. , so the design freedom of the aforementioned components is small
[0005] In addition, U.S. Patent No. 5,672,910 discloses the use of a flat insulating sheet covering the heat sink to increase the creepage distance and space distance, but too long a flat insulating sheet will affect the convection of the heat sink and increase the volume of the package structure; while the U.S. invention The packaging structures disclosed in Patent No. 5,698,899, Japanese Laid-Open Patent No. 06-061375 and Japanese Laid-Open Patent No. 2000-236047 cannot effectively increase the creepage distance and space distance

Method used

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Embodiment Construction

[0035] figure 2 A cross-sectional view of a chip package structure according to an embodiment of the present invention is shown. Figure 3 ~ Figure 8 draw figure 2 Cross-sectional views of various variations of the insulating sheet in .

[0036] Please refer to figure 2 The chip packaging structure 200 of this embodiment includes a substrate 210 , at least one chip 220 , a plurality of leads 230 , a heat dissipation component 240 , an encapsulant 250 and at least one insulating sheet 260 .

[0037] The substrate 210 has a first surface 212 and a second surface 214 opposite to the first surface 212 . The substrate 210 can be a printed circuit board (PCB), a copper-clad ceramic substrate (DCB), an aluminum-clad ceramic substrate (DAB), an insulated metal substrate (IMS), or a lead frame.

[0038] The chip 220 is disposed on the substrate 210 . In this embodiment, there are multiple chips 220 disposed on the first surface 212 of the substrate 210, and can be electrically ...

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Abstract

The invention provides a chip packaging structure, comprising a substrate, at least one chip, a plurality of leads, a cooling component, packaging gel and at least one insulating sheet, wherein, the chip is arranged on the substrate; the leads are electrically connected with the substrate; the at least one chip, the substrate and part of leads are coated with the packaging gel which is provided with a top surface; the cooling component is arranged on top surface of the sealing gel; the at least one insulating sheet is arranged between the cooling component and at least one lead, and provided with a bending line which divides the at least one insulating sheet into a body arranged on the packaging gel and a buckling part extended from the body.

Description

technical field [0001] The present invention relates to a chip packaging structure, and in particular to a chip packaging structure with high voltage protection. Background technique [0002] When designing a chip package structure that requires high voltage input (such as a power module that controls the power supply or an IGBT module that controls the motor drive), in order to comply with safety standards (such as: UL Standard) and ensure the normal operation of the package structure, it is usually necessary Consider the creepage distance and clearance distance between the voltage input terminal (such as a lead) of the package structure and the metal material (such as a heat sink) to avoid conduction between the lead and the heat sink This results in an electrical short circuit and prevents the instantaneous high voltage input from the pin from directly jumping to the low voltage end (ie, the heat dissipation component), thereby endangering the safety of users. [0003] ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/31H01L23/367H01L23/433H01L25/00
CPCH01L2224/48137H01L2924/0002H01L2224/48091H01L2224/73265H01L2224/48247H01L2924/13055H01L2924/13091H01L2924/181H01L2924/00014H01L2924/00H01L2924/00012
Inventor 温兆均陈大容吕保儒吕俊弦
Owner CYNTEC