Inversion of alternate instruction and/or data bits in a computer

Abstract

A basic computer circuit (30) with alternate bits inverted. Two 18-bit registers (32, 34) are connected to ALU (36) to perform ripple-carry addition, wherein 1-high number representation is implemented in the circuit portions corresponding to odd- numbered bit positions, and inverse representation, in even-numbered bit positions. Owing to alternate bit inversion, carry calculation for 1 -bit addition can be performed in only one inverter latency, resulting in a fast 18-bit adder with small die area. Inverted number representation in alternate bit positions can be used in other combinatorial circuits, where an extra inverter stage is conventionally required to adjust the logic level, to reduce latency of operation and die area.

Description

[0001] Related application [0002] This application claims the rights and interests of the co-pending US provisional patent application 60 / 876,379 filed by the same inventor on December 21, 2006, which is incorporated herein by reference in its entirety. Technical field [0003] The present invention relates to the field of electronic computers that perform arithmetic processing and calculations, and more specifically, to the physical representation of binary numbers in computer circuits. Background technique [0004] Digital computers work by manipulating binary numbers (also called true and false logic states or Boolean values) as a sequence of high and low values ​​of physical properties, where the physical properties are usually circuit potential (voltage). By convention, in the entire computer circuit, a high voltage value (or level) is uniformly assigned to represent binary 1, and a low value is assigned to represent binary 0 (here called 1-high representation), or vice versa...

AI Technical Summary

Problems solved by technology

While a number of different techniques are known in the art to perform multi-bit addition (where parallelism (and grouping of bit positions) is exploited in different ways), these techniques all suffer from the dependence of all lower bits of the bit input on Latency (delay time) due to the sum of any bit position (or grouping of bits), or equivalently, a 1-bit addition at any bit position requires a carry from the adjacent lower bit

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