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Dynamic substrate bias system and method for suppressing negative bias temperature instability

A technology of instability and substrate bias, applied in the direction of control/regulation systems, reliability improvement and modification, instruments, etc., can solve the problems of general products and methods without suitable structures and methods, inconvenience, etc.

Inactive Publication Date: 2010-06-09
TAIWAN SEMICON MFG CO LTD
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0004] It can be seen that the reliability of the above-mentioned existing deep sub-micron complementary metal oxide semiconductor components is affected by the instability of negative bias voltage and high temperature, which makes it inconvenient and defective in use, and needs to be further improved.
In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable structure and method for general products and methods to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve

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  • Dynamic substrate bias system and method for suppressing negative bias temperature instability
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  • Dynamic substrate bias system and method for suppressing negative bias temperature instability

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Embodiment Construction

[0037] In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, a dynamic substrate bias that suppresses the high-temperature instability of the negative bias proposed according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. The specific implementation, structure, method, steps, features and effects of the system and method are described in detail below.

[0038] The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. Through the description of the specific implementation mode, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings a...

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Abstract

This invention discloses a system and method for suppressing negative bias temperature instability in PMOS transistors, the system comprises a PMOS transistor having a source connected to a power supply, and a voltage control circuitry configured to output a first and a second voltage level, the first and second voltage levels being different from each other, the first voltage level is lower than the power supply voltage, the second voltage level is equal to or higher than the power supply voltage, wherein when the PMOS transistor is turned on, the first voltage level is applied to a substrate of the PMOS transistor, and when the PMOS transistor is turned off, the second voltage level is applied to the substrate of the PMOS transistor.

Description

technical field [0001] The present invention relates to an integrated circuit design, in particular to a negative bias suppressing method for improving the device performance of a P-channel metal-oxide-semiconductor transistor and the reliability of negative bias high-temperature instability by using a dynamic substrate bias Dynamic substrate biasing systems and methods for high temperature instability. Background technique [0002] For deep submicron complementary metal oxide semiconductors, especially for P-channel metal oxide semiconductor transistors, negative bias temperature instability (Negative Bias Temperature Instability; NBTI) is an important factor affecting device reliability. It is generally believed that the degradation of negative bias high temperature instability is caused by interface traps, and the interface traps are unsaturated silicon dangling bonds. The reaction-diffusion model is one of the physical models that can perfectly explain the negative bias...

Claims

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Application Information

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IPC IPC(8): H03K19/003H03K19/0944
CPCG05F3/205
Inventor 吴伟豪欧东尼
Owner TAIWAN SEMICON MFG CO LTD
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