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Shallow slot isolation process for precisely controlling line width

A shallow trench isolation and precise control technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc. The effects of engraving rework, reducing production costs, and reducing precision requirements

Active Publication Date: 2011-08-24
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This will increase the defects of silicon wafers, resulting in a decrease in yield rate, and also increase the production pressure of lithography machines, resulting in waste of resources

Method used

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  • Shallow slot isolation process for precisely controlling line width
  • Shallow slot isolation process for precisely controlling line width
  • Shallow slot isolation process for precisely controlling line width

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0026] see image 3 , the present invention precisely controls the shallow trench isolation process of the line width, after growing silicon oxide and depositing silicon nitride on the surface of the silicon wafer, it also includes the following steps:

[0027] The first step is to apply photoresist on the surface of the silicon wafer, remove the photoresist in the etching window after exposure and development, and keep the photoresist in the remaining areas.

[0028] The second step is to measure the line width between the etching windows, that is, the photolithography CD of the shallow trench isolation process.

[0029] In the third step, silicon nitride, silicon oxide and part of silicon are etched away in the etching window by using an anisotropic etching process.

[0030] In the fourth step, silicon nitride, silicon oxide and part of silicon are etched in the etching window by using an isotropic etching process.

[0031] Step 5, dry plasma removal of photoresist.

[00...

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PUM

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Abstract

The invention discloses a shallow slot isolation process for precisely controlling line width. The method comprises the following steps: one, coating photoresist on the surface of a silicon chip, exposing etching windows after exposure and development; two, measuring the line width between the etching windows; three, etching silicon nitride, monox and part of silicon on the etching windows; four,removing the photoresist by dry-method plasma; five, peeling off the photoresist through wet-method chemistry; and six, measuring the line width between shallow groove isolation structures. The shallow slot isolation process is characterized in that: the process adds one step between the step three and the step four, and adopts an isotropic etching process to etch the silicon nitride, the monox and the part of silicon on the etching windows. The process can precisely control the characteristic dimension of the shallow slot isolation process, reduces the precision requirement of etching CD, and removes the photoetching rework, thereby reducing production cost.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing method, in particular to a shallow trench isolation (STI) process. Background technique [0002] The shallow trench isolation process is a common process in the manufacture of semiconductor integrated circuits. After growing silicon oxide and depositing silicon nitride on the surface of the silicon wafer, it also includes the following steps: see figure 1 . [0003] The first step is to apply photoresist on the surface of the silicon wafer, remove the photoresist in the etching window after exposure and development, and keep the photoresist in the remaining areas; [0004] Step 2, measuring the line width between the etching windows; [0005] Step 3, using an anisotropic etching process to etch away silicon nitride, silicon oxide and part of silicon in the etching window; [0006] Step 4, dry plasma removal of photoresist; [0007] Step 5, wet chemical stripping of photoresis...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/76H01L21/66
Inventor 吕煜坤孙娟
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP