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Method for forming through hole and double-embedded structure

A technology of graphics and dielectric layers, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as failure, deterioration, and affecting the quality of metal filling, so as to reduce damage and improve the quality of formation

Active Publication Date: 2012-02-29
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Especially in technology nodes below 65nm, the etch stop layer 101 is usually formed of relatively weak nitrogen-doped silicon carbide, and this dishing problem is even more serious
Once this kind of sag problem occurs, it will directly affect the filling quality of the metal in the through hole, and then affect the electrical connection quality in the integrated circuit, so that the performance of the device, such as reliability, will deteriorate or even fail.
[0008] The Chinese patent application with the publication number CN101231968A published on July 30, 2008 discloses a damascene interconnection structure and a dual damascene process, which utilizes carbon tetrafluoride and nitrogen trifluoride gas plasmas for engraving in LRM. Etching gas to solve the problem of recess formation in the underlying dielectric layer due to misalignment in damascene structures
However, this application does not propose an effective solution to the problem of depressions occurring below the sidewalls of the through-holes in the above-mentioned LRM step.

Method used

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  • Method for forming through hole and double-embedded structure
  • Method for forming through hole and double-embedded structure
  • Method for forming through hole and double-embedded structure

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no. 1 example

[0073] The first embodiment of the present invention describes a method for forming a through hole, Figure 6 It is a flow chart of the through hole forming method according to the first embodiment of the present invention, Figure 7 to Figure 10 It is a schematic cross-sectional view of a device describing the process of forming a through hole in the first embodiment of the present invention. Combine below Figure 6 to Figure 10 A first embodiment of the present invention will be described in detail.

[0074] Step 601: Provide a substrate, and etch a stop layer on the substrate, and have a dielectric layer on the etch stop layer.

[0075] Figure 7 is a schematic cross-sectional view of the substrate provided in the first embodiment of the present invention, such as Figure 7 As shown, an etch stop layer 701 and a dielectric layer 702 are formed on a substrate 700 .

[0076] The substrate 700 in this embodiment may be a substrate on which a metal-oxide-semiconductor tran...

no. 2 example

[0109] After the semiconductor process technology enters 0.18 microns, the feature size of the device is further reduced, and the RC delay of the interconnection line gradually becomes the main contradiction affecting the circuit speed. In order to improve this, the process method of making the metal interconnection line structure from metal copper has been adopted. Compared with the traditional aluminum process, the advantage of the copper process is that it has lower resistivity and better conductivity, and the interconnection wires made of it can be made smaller while maintaining the same or even stronger current carrying capacity. more dense. In addition, it also has greater advantages over aluminum processes in terms of electromigration, RC delay, reliability, and lifetime. Due to the characteristics of copper metal not easily etched, the production of copper metal wiring needs to be realized by using a dual damascene structure, and the above-mentioned depression problem ...

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Abstract

The invention discloses a method for forming a through hole, which comprises the following steps: providing a substrate which is provided with an etching stop layer provided with a dielectric layer; defining a through hole graph on the dielectric layer; performing primary etching to form a through hole opening in the dielectric layer till the etching stop layer is exposed; and performing secondary etching, and removing the etching stop layer from the through hole opening, wherein the gas used in the secondary etching comprises an etching reaction gas and an auxiliary gas, the etching reaction gas comprises a fluorine containing gas, and the auxiliary gas comprises a gas of which the mass is smaller than argon. The invention also discloses a corresponding method for forming a double-embedded structure. The method for forming the through hole and the double-embedded structure avoids the problem that the lower part of the side wall of the through hole is sunken, and improves the forming quality of the through hole or the double-embedded structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a through hole and a double damascene structure. Background technique [0002] The manufacture of semiconductor integrated circuits is an extremely complicated process. Its purpose is to reduce the various electronic components and circuits required for a specific circuit on a small-area silicon chip, and each component must be made by appropriate interconnecting wires. Only when they are electrically connected can they perform the desired function. Among them, in order to realize the electrical connection between multilayer circuits on the silicon chip, a large number of through holes need to be fabricated, and the performance of these through holes has an important impact on the overall performance of the circuit. [0003] Figure 1 to Figure 4 It is a schematic cross-sectional view of a device for explaining a conventional via hole for...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/311
Inventor 孙武王新鹏尹晓明
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP