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Method for generating parity-check matrix

A parity check matrix and check node technology, applied in the field of low-density parity check code rearrangement, can solve the problem of not taking into account the short loop effect, affecting the correctness of check node calculation results, etc., to reduce dependencies Effect

Inactive Publication Date: 2010-07-07
MEDIATEK INC
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Problems solved by technology

However, the existing multi-level graph 10, no matter whether VSBP or HSBP is used, does not take into account the short cycle effect, and the short cycle effect may affect the calculation results of the check nodes c1, c2, c3, and c4 correctness

Method used

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  • Method for generating parity-check matrix
  • Method for generating parity-check matrix
  • Method for generating parity-check matrix

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Embodiment Construction

[0014] Certain terms are used in the specification and subsequent claims to refer to particular components. Those of ordinary skill in the art will appreciate that manufacturers may refer to the same component by different terms. This specification and subsequent patent applications do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. "Includes" and "comprising" mentioned throughout the specification and subsequent claims are open-ended terms, so they should be interpreted as "including but not limited to". In addition, the term "coupled" includes any direct and indirect electrical connection means. Indirect means of electrical connection includes connection through other means.

[0015] see figure 2 and image 3 . figure 2 is a flowchart of a method 200 for generating a parity check matrix H' to decode a plurality of underdetermined nodes V1, V2, V3, V4, V5, V6, V7 acco...

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Abstract

A method for generating a parity check matrix to decode a plurality of underdetermined nodes, includes the steps of: determining a plurality of specific nodes according to a predetermined parity check matrix; determining a plurality of weightings corresponding to the plurality of specific nodes; and sorting the plurality of specific nodes according to the plurality of weightings to generate the parity check matrix to store in a storage device. By LDPC rearrangement, the digital data check method is accurate and effective and the dependence in the LDPC decoding is reduced considering shortloop effect.

Description

technical field [0001] The present invention relates to a method for generating parity-check (parity-check) codes, more particularly, to a method for rearranging Low Density Parity-Check (LDPC) codes to generate A method for rearranging LDPC codes. Background technique [0002] In the field of digital data decoding, LDPC codes are used to correct erroneous bits in digital data after transmission through a noisy transmission channel. see figure 1 . figure 1 It is a schematic diagram of the existing multi-level figure 10 for correcting seven-bit input digital data, the seven-bit digital data is bit nodes v1, v2, v3, v4, v5, v6, v7, and the multi-level figure 10 is based on the LDPC code C For error correction, where C is represented by the following matrix: [0003] C = 1 1 0 0 1 ...

Claims

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Application Information

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IPC IPC(8): H03M13/03
CPCH03M13/616H03M13/1137H03M13/114
Inventor 苏育德王诗尧
Owner MEDIATEK INC
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