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Method and device for providing memory model for hardware attributes for transaction executions

A hardware attribute and memory technology, applied in memory systems, machine execution devices, concurrent instruction execution, etc.

Inactive Publication Date: 2015-02-11
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, instructions that set and read these attributes are implemented according to the current memory ordering, which can cause ordering violations.

Method used

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  • Method and device for providing memory model for hardware attributes for transaction executions
  • Method and device for providing memory model for hardware attributes for transaction executions
  • Method and device for providing memory model for hardware attributes for transaction executions

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Embodiment Construction

[0019] In the following description, for example, specific hardware structures for transaction execution, specific types and implementations of access monitors, specific cache implementations, specific types of cache coherency models, specific data granularity, attributes of Numerous specific details of examples such as specific types and specific structures for detecting dependencies are provided in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that these specific details need not be utilized to practice the present invention. In other cases, well-known things such as implementation details of hardware monitors / attributes, transaction demarcation, specific and alternative multi-core and multi-threaded processor architectures, specific compiler methods / implementations, and specific operational details of microprocessors are not described in detail. components or methods so as not to unnecessarily obscure the...

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Abstract

A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.

Description

technical field [0001] The present invention relates to the field of processor execution, and in particular, to the execution of instruction sets. Background technique [0002] Advances in semiconductor processing and logic design have allowed for an increase in the amount of logic that can be present on an integrated circuit device. As a result, computer system configurations have evolved from single or multiple integrated circuits in a system to multiple cores and multiple logical processors present on a single integrated circuit. A processor or integrated circuit typically includes a single processor die, where a processor die may include any number of cores or logical processors. [0003] The ever-increasing number of cores and logical processors on integrated circuits enables more software threads to run concurrently. However, the increase in the number of software threads that can run concurrently raises the issue of synchronizing data shared between the software th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F12/08
CPCG06F11/0751G06F11/3089G06F9/30076G06F11/3471G06F9/3838G06F9/3834G06F11/073G06F2201/885G06F12/0831G06F11/3017G06F11/3037G06F11/0715G06F12/084G06F11/0724
Inventor G·希菲尔S·赖金V·巴辛E·科亨O·马古利斯
Owner INTEL CORP