Device for realizing fixed forwarding delay of V.24 interface multiplexer

Abstract

The invention provides a device for realizing the fixed forwarding delay of a V.24 interface multiplexer. The device comprises a phase lock loop (PLL) frequency doubling / dividing module, an edge / code pattern capturing module, a counter / clock generator module 1, a V.24 / E1 multiplexing module, an E1 interface module for NRZ code / HDB3 code conversion, an E1 interface module for HDB3 code / NRZ code conversion, an E1 clock / frame synchronization recovering module, an E1 / V.24 de-multiplexing module and a counter / clock generator module 2. The device controls delay jitter in transmission from V.24 to E1 to be within 1 mu S by cooperative work among the modules to effectively reduce an end-to-end delay compensation error and realize intranet clock synchronization.

Description

technical field [0001] The invention belongs to the multiplexer fixed forwarding delay technology, in particular to a device for realizing the fixed forwarding delay of a V.24 interface multiplexer. technical background [0002] The principle of the V.24 interface to the framed E1 data multiplexer is: use 1~2 of the 30 data time slots (CAS mode) or 31 data time slots (CCS mode) of the framed E1 to transfer the V The data of the .24 interface is multiplexed to the E1 transmission link, and the V.24 data is taken out and restored from the time slot of the framed E1 in the opposite way at the opposite end. The V.24 signal can be a synchronous signal with a rate of 64kbps or 128kbps, or an asynchronous signal with a rate between 100bps and 19200bps, which can be a standard baud rate or a custom rate. [0003] The V.24 interface conforms to the ITU-T V.24 standard, and the E1 conforms to the ITU-T G.703 and G.704 standards. [0004] The traditional multiplexer can ensure that V...

AI Technical Summary

Problems solved by technology

[0004] The traditional multiplexer can ensure that V.24 data is transmitted on the E1 line without error. The problem is: V.24 data is sampled by 64KHz or 128KHz, and then multiplexed to the designated time slot of E1. In this process, V.24 The time of data transmission is not directly related to the time of E1 frame transmission, so the transmission delay cannot be guaranteed

Traditional multiplexers cannot be used where fixed forwarding delay is required

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