Packet processing device and method by multiple processor cores
一种处理装置、处理方法的技术,应用在多道程序装置、程序控制装置、电数字数据处理等方向,能够解决无法解决、不包含数据包交换机、变更等问题,达到实现线速度的处理、灵活编程、实现编程的效果
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[0052] figure 1 It is a block diagram showing the overall configuration of the packet processing apparatus 101 according to the first embodiment of the present invention.
[0053] The packet processing device 101 is composed of one or more packet processing boards (PPBs) 111, one or more network interfaces (NIFs) 151 each connected to a network, a control board (CB) 141, and a The switch fabric 181 to which they are connected.
[0054] exist figure 1 In the figure, as an example, a packet processing device 101 including n packet processing boards 111 and m network interfaces 151 is shown. But when figure 1 Only three of the n data packet processing boards 111 are denoted as data packet processing boards 111A, 111B and 111C, and only three of the m network interfaces 151 are denoted as network interfaces 151A, 151B and 151C. In the present embodiment, when a general description is given to any one of the packet processing boards 111A to 111C, they are collectively referred ...
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