The application provides a multi-path parallel circuit based on QC-LDPC hard decision decoding
algorithm and an implementation method thereof, and is used for solving the technical problems that the existing circuit based on hard decision GDBF
algorithm consumes too much hardware resource and the
processing speed cannot meet the current high-speed
data transmission. The multi-path parallel circuit comprises parallel P-path hard decision circuits, a first conversion circuit and a second conversion circuit. The hard
decision circuit comprises an offset module, a first storage RAM, a second storage RAM, a second selector, L shift check modules, a calculation module, L+1 energy value storage RAMs, a flip module and a second XOR module. The offset module is used for storing column offset and row offset of a selected check matrix. The shift check module is used for shifting a
code word and obtaining a check subsum. The calculation module is used for calculating the energy value of the
code word, encoding the energy value, and obtaining a maximum energy value. The flip module is used for determining whether to flip according to the energy value of each bit of the
code word and the maximum energy value.