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Clock generation system and clock frequency division module

A technology of clock frequency division and clock frequency divider, which is applied in the direction of electrical components, counting chain pulse counters, pulse counters, etc., and can solve problems such as complex circuit design and worsening of clock skew problems

Inactive Publication Date: 2010-10-13
LINK TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the chip designer uses the known clock generation module to realize the clock gating technique, the circuit design will be very complicated
At the same time, these functional blocks are distributed in different positions on the chip, so the clock skew problem of these gate clock signals will also worsen with the increase of wiring length

Method used

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  • Clock generation system and clock frequency division module
  • Clock generation system and clock frequency division module
  • Clock generation system and clock frequency division module

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Experimental program
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Embodiment Construction

[0012] figure 2 A typical flow chart using a hardware description language to implement a chip design is shown, which is configured to implement the invention. refer to figure 2 , in step S20, the system designer formulates the specifications of the chip. In step S22, the chip designer generates and verifies a register-transfer level netlist (RTL netlist). In step S24, the chip designer generates a logic gate-level netlist through a synthesis tool and verifies it. In step S25, the chip designer generates a physical design through a place and route tool. Each step of the process is further described below.

[0013] Firstly, before developing the chip, the system designer will set some specifications such as function, operating speed, interface specification, ambient temperature and power consumption according to the application occasion of the chip. When the specification is completed, the system designer will divide the chip into several functional blocks according to t...

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Abstract

The invention relates to a clock generation system and a clock frequency division module. The clock generation system comprises a clock frequency divider, a first function block and a second function block, wherein the clock frequency divider is used for outputting the clock signal with different frequencies; the first function block comprises a first clock gating unit and a first logic circuit, and the second function block comprises a second clock gating unit and a second logic circuit; the first clock gating unit and the second clock gating unit are respectively arranged in the first function block and the second function block in logic and are respectively arranged on the position approaching to the clock frequency divider as much as possible in physical layout.

Description

technical field [0001] The invention relates to a clock generation system and a clock frequency division module, specifically to a clock generation system with a distributed architecture. Background technique [0002] In the design of CMOS VLSIs, such as Application Specific Integrated Circuits (ASICs), the clock signal has a decisive influence on the performance of the chip. If the chip designer does not carefully plan the clock distribution (clock distribution) of the clock signal to each logic sub-block during design, then the clock skew (clock skew), that is, the maximum delay and minimum delay between the clock endpoint and the clock sink The difference will degrade the performance of the chip and may cause the system to fail. In addition, the power loss of the clock distribution network usually accounts for 20% to 50% of the overall power loss due to the need to maintain high-speed operation and driving force on the path between the clock endpoint and the clock sink t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K23/66
Inventor 叶时益
Owner LINK TECH INC