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Runtime programmable BIST for testing a multi-port memory device

一种存储器、多端口的技术,应用在静态存储器、数字存储器信息、信息存储等方向,能够解决测试程序无法存储器采用等问题

Active Publication Date: 2010-11-03
SYNOPSYS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, if the test program is hardwired into the test equipment, new test programs created after the test equipment is equipped with a multi-port memory device cannot be used in memory.

Method used

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  • Runtime programmable BIST for testing a multi-port memory device
  • Runtime programmable BIST for testing a multi-port memory device
  • Runtime programmable BIST for testing a multi-port memory device

Examples

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Embodiment Construction

[0032] The following description is given to enable one skilled in the art to make and use the embodiments, and is presented in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not limited to the illustrated embodiments, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0033] The data structures and code described in this detailed description are typically stored on a computer readable storage medium, which can be any device or medium that can store code and / or data usable by a computer system. Computer-readable storage media include, but are not limited to, volatile memory, nonvolatile memory, magnetic and optical storage devices ...

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Abstract

The invention discloses a runting programmable BIST for testing a multi-port memory device. One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence.

Description

technical field [0001] The present disclosure generally relates to electronic design automation. More specifically, the present disclosure relates to methods and apparatus for testing multi-port memory devices for realistic faults. Background technique [0002] As multiprocessor computing systems become more common, multiport memory devices are becoming more common. Multi-port memory devices play an important role in synchronizing operations performed by two or more microprocessors of a computing system. Therefore, it is very important that the multi-port memory device be fully tested for failure before it is integrated into a multi-processor computing system. [0003] However, testing multi-port memory devices presents unique challenges that cannot be addressed by general methods and apparatus for testing single-port memory devices. More specifically, real-world faults can occur in multi-port memory devices, for example, real-world faults are activated when two ports of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/12G11C29/38G11C29/18
CPCG11C29/16G11C8/16G11C29/56
Inventor M·尼科莱迪斯S·鲍托布扎
Owner SYNOPSYS INC