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Equivalent strain memory method for preparing strain channel CMOS

A technology of equivalent strain and strain channel, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve the problems of insignificant performance improvement of large-scale devices

Inactive Publication Date: 2014-02-12
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The purpose of the present invention is to solve the shortcomings that the conventional local strain technology that has been adopted at present is restricted by the feature size, and the strain does not significantly improve the performance of large-scale devices, and the SMT technology can only provide a memory surface. Insufficient strain, a special proposal An equivalent strain memory method that is not limited by size and can provide two different types of strained channels for CMOS devices, which is used to prepare advanced transistors with strained channels to improve the output performance of CMOS devices and improve the frequency of devices performance

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  • Equivalent strain memory method for preparing strain channel CMOS
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  • Equivalent strain memory method for preparing strain channel CMOS

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Embodiment 1

[0019] Embodiment 1. Embodiment 1 is a memory method for realizing tensile strain in the channel direction, which can be used to manufacture tensile strain channel NFET devices. refer to Figure 4a to Figure 4f , and its key steps will be described in detail.

[0020] Figure 4a It shows that regions for preparing different devices are isolated on the semiconductor material 110 , and NFET and PFET devices are respectively prepared on both sides of the dielectric isolation 114 .

[0021] Figure 4b It shows that a dielectric layer 106 is grown on the semiconductor layer, and this dielectric layer can be used to protect the surface and can also be used as an etching stop layer. The growth method can adopt the method of deposition, after that, it needs to be removed during the device manufacturing process; it can also be used to thermally grow a high-quality dielectric layer and use it as the gate dielectric layer of the device (at this time, it is figure 1 102A in).

[0022...

Embodiment 2

[0027] Embodiment 2, Embodiment 2 is a memory method for achieving compressive strain in the channel direction, which can be used to manufacture a compressively strained channel PFET device. refer to Figure 5a to Figure 5e , and its key steps will be described in detail.

[0028] exist Figure 5a Among them, an insulating layer may be separated between the substrate 100 and the semiconductor material 110 to form an SOI structure; or a heterogeneous semiconductor material different from the substrate material is directly epitaxially grown on the substrate; or the semiconductor material is directly used as the substrate. Based on a process similar to the foregoing, it is possible to form Figure 5a The medium layer 106 in, its function is also the same as that of embodiment 1 Figure 4b , forming figure 1 102B in.

[0029] Figure 5b It shows that after the resist mask 107 is used to protect the part where the NFET device will be made and the part where the PFET device wi...

Embodiment 3

[0034] Embodiment 3. Embodiment 3 is a method for realizing tensile strain and compressive strain respectively in the channel direction, which can respectively manufacture NFET with tensile strain channel and PFET with compressive strain channel for use in CMOS technology. refer to Figure 6a to Figure 6g , and its key steps will be described in detail.

[0035] Based on a process similar to the aforementioned, Figure 6a It is shown that the isolation layer 114 has been prepared on the semiconductor material 110 on the substrate 100 , and a dielectric layer 106 with the same function is formed by using a similar aforementioned process.

[0036] Figure 6b It is shown that after patterning the region where the PFET device will be fabricated is protected by a resist mask 107, a suitable dielectric layer 108A with high intrinsic tensile stress is deposited. The high intrinsic stress in the dielectric layer can be effectively transferred to the underlying semiconductor substra...

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Abstract

The invention discloses an equivalent strain memory method for preparing a strain channel CMOS (complementary metal oxide semiconductor), and relates to manufacture of integrated circuits, in particular to a strain technique introduced by the equivalent strain memory method for providing tensile strain and compressive strain for FET (field effect transistor) and PFET (P-type field effect transistor) devices in the CMOS respectively. In the memory method provided by the invention, strain is introduced on the surface of a substrate through a surface shearing stress, the magnitude of the strain is changed along with different longitudinal depths but not changed along with the change of the transverse dimension in the surface, and equivalent strain along the channel direction is kept through normal stress of the side wall. Under the condition that the characteristic dimension of the transistor manufactured by using the method is several microns, the channel still has large strain and can improve the frequency characteristics of devices and circuits.

Description

technical field [0001] The invention relates to the manufacture of integrated circuits, especially the strain technology introduced by the equivalent strain memory method, which provides tensile strain and compressive strain for NFET and PFET devices in complementary metal oxide semiconductor field effect transistor CMOS, thereby improving the device and The frequency characteristics of the circuit. Background technique: [0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most important basic active devices in integrated circuits. The CMOS formed by the complementarity of N-type MOSFET and P-type MOSFET is the constituent unit of deep submicron VLSI. As we all know, the main means to increase the speed of MOSFET devices and reduce product costs is to scale down the feature size. However, as the device size enters the deep submicron field, further reduction in size will be limited by potential limitations such as materials, processes and various ph...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
Inventor 于奇宁宁王向展杜江峰杨洪东李竞春
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA