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Transistor and fabrication method thereof

A technology of transistors and manufacturing methods, applied in the field of semiconductor circuits

Active Publication Date: 2012-07-18
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, reducing component size often presents new challenges to overcome

Method used

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  • Transistor and fabrication method thereof
  • Transistor and fabrication method thereof
  • Transistor and fabrication method thereof

Examples

Experimental program
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Effect test

Embodiment Construction

[0054] Known transistors have stressed channels. This known transistor has a SiGe source and a SiGe drain. Each SiGe source and drain has a single stressor layer. Each stressed SiGe source and drain has a {111} facet in the substrate. The {111} crystal plane forms a V-shape in the substrate and is fabricated by a wet etching process, wherein the wet etching utilizes the {111} crystal plane as an etching stop layer.

[0055] It is known that SiGe source / drain can be disposed between two adjacent transistor gates. If the gap between the gates of two adjacent transistors becomes smaller, the volume of the SiGe source / drain will also become smaller because of the {111} crystal plane. And the shrinking silicon germanium source / drain may not be able to provide the compressive stress needed for the transistor channel.

[0056] Based on the above reasons, it is necessary to provide a transistor with a composite stress structure, an integrated circuit, and the above manufacturing me...

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Abstract

The invention provides a transistor and a fabrication method thereof. The transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region.At least a portion of the second strain region is disposed within the substrate. The transistor comprises a composite stress structure to provide the compression or stretching stress required by the channel of the transistor and increase the electric expression of the transistor.

Description

technical field [0001] The present invention relates to the field of semiconductor circuits, and in particular to a transistor with a composite stress structure, an integrated circuit and the above manufacturing method. Background technique [0002] An integrated circuit is formed by forming one or more elements (eg, circuit elements) on a semiconductor substrate using process technology. Since the introduction of components decades ago, with the advancement of process technology and materials, the geometries of semiconductor components have continued to shrink. For example, current process technologies produce device geometries (eg, the smallest device achievable using this process) (or line width) of less than 90 nm. However, reducing the size of components often presents new challenges to overcome. [0003] When the size of the microelectronic device (microeletronic device) shrinks below 65nm, the problem of electronic efficiency will affect the performance of the devic...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/66636H01L29/7848H01L29/7834H01L29/66628H01L29/165H01L29/6659H01L21/3065
Inventor 郑振辉宋学昌陈冠宇林宪信冯家馨
Owner TAIWAN SEMICON MFG CO LTD