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MOS gate power semiconductor device

A technology of power semiconductors and semiconductors, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve problems such as dead-time harmonic increase and inverter performance degradation, so as to prevent drive circuit failure and prevent Deterioration and/or damage, weight reduction effect

Inactive Publication Date: 2011-04-06
TRINNO TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the extension of the dead time results in the increase of harmonics caused by the distortion of the inverter's output waveform, thus degrading the performance of the inverter

Method used

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Embodiment Construction

[0048] While the invention can be modified in various forms, specific embodiments will be described and shown in the drawings. However, the embodiments are not intended to limit the present invention, but it should be understood that the present invention includes all improvements, equivalents and replacements belonging to the spirit and technical scope of the present invention. When it is judged that a detailed description of known technology related to the present invention obscures the gist of the present invention, the detailed description will be omitted.

[0049] Various elements may be described using terms such as 'first' and 'second', but the elements are not limited by the terms. The terms are only used to distinguish one element from another.

[0050] Terms used in the following description are used to describe specific embodiments only, but are not intended to limit the present invention. A singular expression includes a plural expression as long as it can be cle...

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Abstract

A MOS-gate power semiconductor device is provided which includes: one or more P-type wells formed under one or more of a gate metal electrode and a gate bus line and electrically connected to an emitter metal electrode; and one or more N-type wells formed in the P-type well and electrically connected to one or more of the gate metal electrode and the gate bus line. According to this configuration, it is possible to suppress deterioration and / or destruction of a device due to an overcurrent.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly, to a MOS-gate power semiconductor device. Background technique [0002] Semiconductor devices such as Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are mainly used as switching devices in the field of power electronics applications. That is, semiconductor devices are used as semiconductor switching devices in power electronics applications such as H-bridge inverters, half-bridge inverters, three-phase inverters, multi-level inverters, and converters. [0003] However, in a power electronic circuit including a semiconductor switching device (ie, a semiconductor device used as a semiconductor switching device), the semiconductor switching device may be degraded or damaged by an overload current generated by failure of a driving circuit system. Therefore, it is necessary to avoid such a failure caused by an overloa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/102H01L27/105
CPCH01L29/8611H01L29/7395H01L27/0705H01L2224/0603H01L2924/13055H01L2924/13091H01L2924/00H01L21/041
Inventor 吴侊勋秋秉镐金秀圣尹钟晚
Owner TRINNO TECH