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Method for manufacturing lattice graded buffer layer

A graded buffer layer and graded layer technology, applied in the field of semiconductors, can solve the problems of high penetration dislocation density on the structure and device surface, the influence of heterojunction material interface materials and device performance, and the inability to eliminate mismatch well, etc. Achieve the effects of reducing dependencies, overcoming performance degradation, and improving efficiency

Active Publication Date: 2013-03-13
CHINA ELECTRONIC TECH GRP CORP NO 18 RES INST +1
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Problems solved by technology

However, due to the existence of residual compressive strain in the graded layer, the lattice constant of the surface of the graded layer is usually smaller than the lattice constant to be controlled, so the threading dislocation density on the surface of the structure and device is still very large, which cannot be well eliminated The impact of mismatch; at the same time, when the top material of the graded layer is different from the material above it, the difference in the interface of the heterojunction material will also have a great impact on the performance of the material and the device
[0004] Therefore, the existing lattice matching growth technology can no longer meet the needs of various new semiconductor devices represented by high-efficiency solar cells in the future, and technological innovation must be sought in lattice mismatching technology

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  • Method for manufacturing lattice graded buffer layer
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preparation example Construction

[0025] A method for preparing a lattice gradient buffer layer, the steps are:

[0026] Step (1): use germanium (Ge) single crystal as substrate 11; the substrate material can be germanium, silicon, and III-V and II-VI group materials or their combination, including gallium arsenide, indium phosphide , Gallium phosphide, gallium nitride, gallium antimonide, etc.; the surface of the substrate can have (100), (110) or (111) crystallographic directions, or other exponential plane directions, and include those in the above directions to other directions Deflection angle of 0-15 degrees.

[0027] Step (2): Use existing epitaxial techniques such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) and liquid phase epitaxy (LPE) to perform epitaxial growth of materials; in order to make the core functional layer of the present invention— —The structure of the lattice-graded buffer layer is not affected by the defects of the substrate. First, a layer of material...

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Abstract

The invention relates to a method for manufacturing a lattice graded buffer layer, which comprises the following steps of: (1) using a commercial germanium single crystal, arsenide gallium single crystal or indium phosphide single crystal as a substrate; (2) epitaxially forming a layer of material in lattice matching with the substrate material as a nucleation layer by utilizing epitaxial technology; (3) epitaxially growing a lattice graded layer on the nucleation layer until the lattice of the material of a top layer has an ideal lattice constant or a lattice constant slightly lower than the ideal lattice constant, wherein the lattice graded layer consists of a plurality of indium gallium arsenide materials with gradually increased components; (4) epitaxially forming a layer of indium gallium arsenide material with the lattice constant more than the ideal lattice constant on the lattice graded layer as a lattice overshoot layer; and (5) epitaxially forming a layer of material which has the lattice constant equal to the ideal lattice constant and is the same as that grown on an adjacent upper layer thereof as the lattice buffer layer. The method solves the problem of influence of device appearance degradation caused by lattice mismatching between a conventional epitaxial material and the substrate, and can effectively control threading dislocation density on the surface of a device.

Description

Technical field [0001] The invention belongs to the field of semiconductor technology, and relates to the structure and manufacturing method of a semiconductor device, in particular to a method for preparing a lattice gradient buffer layer. Background technique [0002] Since the 1970s, with the gradual development and maturity of epitaxial equipment such as liquid phase epitaxy (LPE), metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE), today’s various semiconductor devices are A commercially available epitaxial substrate is prepared by epitaxial growth. This growth method determines that in most cases, the epitaxial material must maintain lattice matching with the epitaxial substrate, otherwise internal stress will be generated due to lattice mismatch, resulting in a lot of misfit dislocations and penetration inside the crystal Dislocation. Because the dislocation destroys the translational symmetry of the crystal, there are a large number of deep...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): C30B25/16
Inventor 刘如彬王帅孙强孙彦铮
Owner CHINA ELECTRONIC TECH GRP CORP NO 18 RES INST
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