Method for critical dimension shrink using conformal PECVD films

Abstract

A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant.

Description

technical field [0001] Embodiments of the present invention relate to semiconductor manufacturing methods. More specifically, embodiments of the invention relate to methods for reducing critical dimensions of semiconductor devices. Background technique [0002] The semiconductor industry has followed Moore's Law for more than half a century. Moore's Law means that the density of transistors on an integrated circuit will double approximately every two years. As the semiconductor industry continues to evolve by this rule, smaller features will need to be patterned on the substrate. Stacked transistors are currently produced in sizes of 50 to 100 nanometers (nm). Components at 45nm can now be produced and efforts are underway to design components at 20nm or smaller. [0003] As components shrink to such a small size, existing lithography processes face difficulties in producing the required critical dimension (CD) patterns. The patterning tools used to make vias 100nm or wi...

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Problems solved by technology

[0003] As components shrink to such a small size, existing lithography processes struggle to produce the required critical dimension (CD) patterns

Patterning tools used to make vias at 100nm or wider typically cannot make smaller vias

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