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Scan chain-based method for testing memory

A memory testing and scan chain technology, applied in the field of memory testing based on scan chain, can solve problems such as inability to locate, test, and inability to function module circuits, and achieve the effect of improving coverage.

Active Publication Date: 2011-04-27
FUZHOU ROCKCHIP SEMICON
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Problems solved by technology

However, in the actual chip, it is found that errors may occur in these serial shift-related ports of the register. Once an error occurs in the serial shift process, not only the functional module circuit cannot be tested, but the existing test vectors cannot Locating where the serial shift went wrong

Method used

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  • Scan chain-based method for testing memory

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Embodiment Construction

[0026] A memory test method based on scan chains, such as figure 2 As shown, the specific description is as follows:

[0027] Step 100: Tetramax (an eda tool that automatically generates scan chain test vectors) generates scan chain test vectors; the first test vector of Tetramax usually only has serial shifting, that is, only serial shifting is performed into -> serial The shift out operation is used to test the correctness of the serial shift. The usual pattern of this vector is 00110011...,

[0028] Step 200: start the first test vector;

[0029] Step 300: serial shift input;

[0030] Step 400: Serial shift output;

[0031] Step 500: If this test vector is passed, the test will turn to the vector with parallel capture mode (ie step 600); and if the port (CK / SI / SE / Q) of the scan chain has stuck-at-0 or stuch- At-1 error, the correct output will not be seen at the output end of the chain, and go to step 700;

[0032] Step 600: Test other vectors with parallel capture; ...

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Abstract

The invention provides a scan chain-based method for testing memory. The method comprises the following steps: firstly, a first test vector of Tetramax generally carries serial shift, if the test vector is passed, the test can be turned to a vector carrying a parallel capture mode; if the port of the scan chain has an error, the port or the type which has error is necessary to be identified; by the parallel capture mode, a test vector is implanted by adopting a dichotomy method; and the test output of a shift vector is observed, and the dichotomy method is used for thining constantly, until an invalid register is accurately positioned. By the function of parallel capture, the test vector can be implanted in the scan chain according to requirement, so that the position of serial shift error can be quickly and effectively positioned, and the coverage rate of test can be greatly improved.

Description

【Technical field】 [0001] The invention relates to the field of IC testing, in particular to a memory testing method based on scan chains. 【Background technique】 [0002] Scan chain technology can effectively detect various errors in the chip manufacturing process, so it is widely used in the testing process after the chip wafer leaves the factory. The test process of the scan chain is composed of a series of test vector sets. For each test vector, it can basically be divided into three steps: serial shift in (shift in), parallel capture (capture) and serial shift out (shift out). The serial shift-in process serially shifts the data required for the next phase of parallel capture into the registers in the scan chain, and the serial shift-out serially shifts the parallel captured data out of the scan chain to external pins for observation and comparison. [0003] The main purpose of the scan chain test is to ensure the correctness of the functional modules after passing the ...

Claims

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Application Information

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IPC IPC(8): G11C29/44
Inventor 杨伟建
Owner FUZHOU ROCKCHIP SEMICON
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