Circuit structure of differential comparator
A differential comparator and circuit structure technology, applied in the direction of electrical pulse generator circuits, differential amplifiers to generate pulses, etc., can solve the problems of reducing the sensitivity of the comparator, high sensitivity and high speed cannot be obtained at the same time, etc., to improve reliability and sensitivity. Effect
Active Publication Date: 2012-10-03
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
However, in the existing comparators, in order to achieve high sensitivity requirements, the speed of the comparator is often sacrificed, and in order to achieve high speed, the sensitivity of the comparator is often reduced
In other words, in existing comparators, high sensitivity and high speed cannot be obtained at the same time
However, with the rapid development of the electronic industry, the performance requirements for comparators are getting higher and higher. Comparators with high sensitivity and high speed are very much needed in many occasions. The existing comparators can no longer meet the needs of these occasions.
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[0008] The invention discloses a differential comparator circuit structure, as shown in the accompanying drawings, a reference current Iref is connected to the gate and drain of the first NMOS transistor M1, and the gates of the second and third NMOS transistors M2 and M3 , the drain of the second NMOS transistor M2 is connected to the source of the fourth NMOS transistor M4, the drain of the third NMOS transistor M3 is connected to the source of the fifth NMOS transistor M5, the drain of the fourth NMOS transistor M4 and the sixth , the sources of the seventh NMOS transistors M6 and M7 are connected together, the drains of the fifth NMOS transistor M5 and the sources of the eighth and ninth NMOS transistors M8 and M9 are connected together, the gate of the fourth NMOS transistor M4 is connected to The gate of the eighth NMOS transistor M8 is connected to serve as the second input terminal VRP of the differential reference level, the gate of the fifth NMOS transistor M5 is conn...
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The invention discloses a circuit structure of a differential comparator, wherein M4 and M5 ensure the identical current which flows through the M2 and M3; M6-M9 pre-amplify an input signal; the difference of the voltage is converted into the current difference of M10 and M11; M12 and M13 copy the current of M11 and M10 and convert the current difference into the voltage difference of VN1 and VP2; and the M21, M22, M15 and M16 amplify and output the voltage difference quickly. According to the circuit structure, the differential comparator greatly improves the reliability and sensitivity of the comparator under the condition that the speed of the differential comparator is constant.
Description
technical field [0001] The invention relates to a circuit structure, in particular to a differential comparator circuit structure. Background technique [0002] In the design of integrated circuits, comparators are a commonly used circuit element. There are also many kinds of comparator structures, which are suitable for different occasions, some require high sensitivity, and some require high speed. However, in the existing comparators, in order to meet the requirement of high sensitivity, the speed of the comparator is often sacrificed, and in order to achieve high speed, the sensitivity of the comparator is also often reduced. That is to say, in the existing comparators, high sensitivity and high speed cannot be obtained at the same time. However, with the rapid development of the electronic industry, the performance requirements for comparators are getting higher and higher. Comparators with high sensitivity and high speed are very much needed in many occasions. The ex...
Claims
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IPC IPC(8): H03K3/023
Inventor 周平骆川
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP