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Semiconductor device

A semiconductor and transistor technology, which is applied in the technical field of effective suppression, can solve problems such as the increase of circuit area, and achieve the effect of suppressing the deviation of gate length, realizing layout design and free layout design.

Inactive Publication Date: 2014-05-14
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this case leads to an increase in the circuit area

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0035] figure 1 It is a schematic diagram of the layout pattern of the semiconductor device according to the first embodiment. exist figure 1 In , the layout of the gate pattern and the diffusion region is shown, and the cell boundary is shown by a solid line (the same applies to other figures). Here, the gate pattern refers to a pattern formed in a layer used as a gate electrode of a transistor, and is manufactured using a material such as polysilicon. The transistor is composed of a gate pattern and a diffusion region, and a portion of the gate pattern sandwiched by the diffusion region functions as a gate of the transistor. Such as figure 1 As shown, the standard cell C1 as the first cell has gates extending in the Y direction (the up-down direction in the figure) as the first direction and arranged at the same pitch in the X direction (the left-right direction in the figure) as the second direction. Patterns G1, G2, G3. The width of the gate patterns G1 , G2 , G3 i...

Embodiment approach 2

[0044] Figure 5 It is a schematic diagram of a layout pattern of a semiconductor device according to the second embodiment. Figure 5 composition and figure 1 Almost the same, in the end portion region R1 , the same shape regularity is maintained with respect to the end portions e1 , e2 , e3 and the opposing end portions eo1 , eo2 , eo3 . However, the internal composition of the standard cell C2 is the same as figure 1 different.

[0045] exist Figure 5 , the standard cell C2 has a large and single gate pattern G5 as the first gate pattern. The width of the gate pattern G5, that is, the gate length L3 of the transistor T3 is set larger than the gate length L1 of the transistor T1. Furthermore, the gate pattern G5 includes a plurality of protruding portions 5 b protruding toward the standard cell C1 in the Y direction, and the protruding portions 5 b constitute opposing terminal portions eo2 and eo3 . That is, the end portion of the gate pattern G5 on the side of the ...

Embodiment approach 3

[0053] Figure 7 It is a schematic diagram of a layout pattern of a semiconductor device according to the third embodiment. Figure 7 composition and figure 1 Almost the same, in the end portion region R1 , the same shape regularity is maintained with respect to the end portions e1 , e2 , e3 and the opposing end portions eo1 , eo2 , eo3 . However, the internal composition of the standard cell C2 is the same as figure 1 different.

[0054] exist Figure 7 Among them, the standard cell C2 has a single gate pattern G8 as the first gate pattern. The gate pattern G8 is a dummy pattern, and has a pattern main body 8a extending in the X direction, and a plurality of protrusions 8b protruding from the pattern main body 8a toward the standard cell C1 in the Y direction. And this protruding part 8b comprises opposing terminal part eo1, eo2, eo3. That is, the gate pattern G8 has a so-called crown shape. Furthermore, in the transistor arrangement region R2, the transistor T5 whic...

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PUM

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Abstract

A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

Description

technical field [0001] The present invention relates to the layout of semiconductor devices, and more particularly, to a technique effective in suppressing the optical proximity effect. Background technique [0002] In the manufacturing process of semiconductor integrated circuits, the photolithography process including resist application, exposure, and development; the etching process for patterning elements using a resist mask; and resist removal are generally repeated. process to form an integrated circuit on a semiconductor substrate. When performing exposure in the photolithography process, if the pattern size is below the exposure wavelength, the error between the layout size during design and the pattern size on the semiconductor substrate increases due to the optical proximity effect caused by the influence of diffracted light. [0003] Also, in a semiconductor integrated circuit, the gate length of a transistor is an important factor determining its performance. T...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/82
CPCH01L27/0207
Inventor 中西和幸田丸雅规
Owner SOCIONEXT INC