High-density SIP (system in package) method of chip

Abstract

The invention relates to a high-density SIP (system in package) method of a chip. The method comprises the following steps: forming a glue layer on a support plate, wherein the shape and position of the glue layer correspond to the shapes of the functional surfaces of packaged devices and the fit positions of the packaged devices on the support plate; sticking the functional surfaces of a chip and passive devices to the glue layer; forming a material sealing layer on the surface of the support plate with the chip and the passive devices, and packaging and curing; and removing the support plate and the glue layer. Compared with the prior art, the high-density SIP method has the following beneficial effects: the chip and the passive devices are integrated and then packaged together, thus forming the final package product with the integral system function instead of the single chip function. In addition, the shape and position of the glue layer formed on the support plate correspond to the shapes of the functional surfaces of the packaged devices and the fit positions of the packaged devices on the support plate, thus being convenient for positioning the chip in the sticking process and avoiding difficult stripping or large-area cleaning in the subsequent process.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a high-density system-level chip packaging method. Background technique [0002] Wafer Level Packaging (WLP) technology is a technology that performs packaging and testing on the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is exactly the same as that of the bare chip. Wafer-level chip-scale packaging technology has completely subverted traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic Leadless Chip Carrier), etc. , small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology has reached a high degree of miniaturization, and the cost of the chip is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is a...

AI Technical Summary

Problems solved by technology

[0004] The final product packaged and manufactured according to the above method has only a single chip function

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