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Highly integrated wafer fan-out packaging structure

A technology with high integration and packaging structure, which is applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of single chip functions, and achieve the effects of avoiding warping, reducing internal stress, and improving quality

Active Publication Date: 2013-10-02
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The final product packaged and manufactured according to the above method has only a single chip function

Method used

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  • Highly integrated wafer fan-out packaging structure
  • Highly integrated wafer fan-out packaging structure
  • Highly integrated wafer fan-out packaging structure

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Embodiment Construction

[0028] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

[0029] Secondly, the present invention is described in detail by means of schematic diagrams. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams are only examples, which should not limit the protection scope of the present invention.

[0030] The packaging structure in the prior art only has a single chip function. To realize complete system functions, it is necessary to add peripheral circuits including various capacitors, inductors or resistors to the...

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Abstract

The invention relates to a highly integrated wafer fan-out packaging structure, comprising a to-be-packaged unit, chips and a passive device, wherein the to-be-packaged unit has a function surface; a material-sealing layer is formed on a surface opposite to the function surface of the to-be-packaged unit; the material-sealing layer carries out packaging curing over the to-be-packaged unit; and a groove is arranged between the to-be-packaged units corresponding to the material-sealing layer surface. Compared with the prior art, the highly integrated wafer fan-out packaging structure of the invention firstly integrates chips and passive devices and then carries out packaging, and is a final packaged product having overall system function, instead of single chip function. Furthermore, in the structure, the entire packaging of the material-sealing layer is decomposed into a plurality of to-be-packaged units, and the internal stress of the material-sealing layer is reduced via the groove between the to-be-packaged units, thereby avoiding warpage of material-sealing layer in the subsequent process of wafer packaging and improving the quality of finished wafer packaging product.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a highly integrated wafer fan-out packaging structure. Background technique [0002] Wafer Level Packaging (WLP) technology is a technology that performs packaging and testing on the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is exactly the same as that of the bare chip. Wafer-level chip-scale packaging technology has completely subverted traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic Leadless Chip Carrier). Small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology has reached a high degree of miniaturization, and the cost of the chip is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is a te...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/16H01L23/495H01L23/31
CPCH01L2224/24195H01L24/18H01L21/568H01L24/96H01L2224/04105H01L2224/12105H01L2924/1815H01L2924/3511H01L2224/19H01L2924/00H01L2924/00012
Inventor 陶玉娟石磊沈海军
Owner NANTONG FUJITSU MICROELECTRONICS
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