Method for encapsulating high-integration wafer fan-out

Abstract

The invention relates to a method for encapsulating high-integration wafer fan-out, comprising the following steps of: forming a cementing layer on a carrier plate; attaching the functional surface of a unit which is encapsulated and consists of a chip and a passive device on the cementing layer; forming a sealing layer on one surface of the carrier plate, on which the chip and the passive deviceare attached, carrying out encapsulation and solidification, and arranging a groove between the surface of the sealing layer and the encapsulated unit; and removing the carrier plate and the cementing layer. Compared with the prior art, the method for encapsulating the high-integration wafer fan-out, which needs to be legally protected, sequentially carries out the steps of integration and encapsulation on the chip and the passive device so that the final encapsulated product having the integral system function rather than the single chip function can be formed. Besides, the method decomposesthe overall encapsulation of the encapsulating layer into a plurality of small encapsulation blocks so as to reduce the inner stress of the encapsulating layer, thus preventing the sealing layer fromgenerating buckling deformation in the subsequent process of wafer encapsulation and improving the quality of finished products of encapsulated wafers.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a highly integrated wafer fan-out packaging method. Background technique [0002] Wafer Level Packaging (WLP) technology is a technology that performs packaging and testing on the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is exactly the same as that of the bare chip. Wafer-level chip-scale packaging technology has completely subverted traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic Leadless Chip Carrier). Small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology has reached a high degree of miniaturization, and the cost of the chip is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is a techn...

AI Technical Summary

Problems solved by technology

[0004] The final product packaged and manufactured according to the above method has only a single chip function

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