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Three-dimensional system level packaging method

A system-level packaging, three-dimensional technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of unsuitable multi-layer packaging structure, and achieve the effect of high integration

Active Publication Date: 2014-05-28
NANTONG FUJITSU MICROELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, the above method is not suitable for the manufacture of multi-layer packaging structures with complex wiring connections

Method used

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Embodiment Construction

[0019] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

[0020] Secondly, the present invention is described in detail by means of schematic diagrams. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams are only examples, which should not limit the protection scope of the present invention.

[0021] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0022] Such as figure 1 and figure 2 As shown, in one embodiment of the presen...

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Abstract

The invention relates to a three-dimensional system level packaging method, which comprises the following steps: providing a carrying board; forming a cementing layer on the carrying board; sticking a chip or a chip and a passive device on the cementing layer; forming a first material sealing layer, and exposing a bonding pad in the chip in a first chip layer or the bonding pads of the chip and the passive device; forming a first micro-through hole in the first material sealing layer; forming first longitudinal metal wiring in the first micro-through hole; forming a first wiring layer on the first material sealing layer; and forming a multi-layer chip layer on the first material sealing layer. Compared with the prior art, the three-dimensional system level packaging method can form a finally packaged product containing an integral system function rather than a single chip function, thereby reducing the interference factors of internal resistance of a system, inductance and the like. In addition, a more complex multi-layer interconnection structure can be formed, and the wafer level packaging with higher degree of integration can be realized.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a three-dimensional system-in-package method. Background technique [0002] Wafer Level Packaging (WLP) technology is a technology that performs packaging and testing on the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is exactly the same as that of the bare chip. Wafer-level chip-scale packaging technology has completely subverted traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic Leadless Chip Carrier), etc. , small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology has reached a high degree of miniaturization, and the cost of the chip is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is a tech...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/98H01L21/56H01L21/60
CPCH01L24/82H01L2224/04105H01L2224/12105H01L2224/32145H01L2224/32225H01L2224/73267H01L2224/92244H01L2924/15311H01L2924/19105
Inventor 陶玉娟石磊王洪辉
Owner NANTONG FUJITSU MICROELECTRONICS
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