Semiconductor device and manufacturing method thereof
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., and can solve problems such as large stress
Active Publication Date: 2013-11-06
TAIWAN SEMICON MFG CO LTD
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- Summary
- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
As such, due to the relatively high stress at the junction between the post and the bump electrode, cracks often occur in the bonded area between the bump electrode / post and the solder ball / solder bump
Method used
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Embodiment Construction
[0020] The present invention will provide many different embodiments to illustrate different features of the present invention. However, it should be noted that the construction and configuration of each specific embodiment will be described in detail below to illustrate the spirit of the present invention, but these embodiments are not intended to limit the present invention.
[0021] Embodiments disclosed herein relate to the use of conductive pillars in semiconductor devices. As described below, embodiments disclosed herein use a conductive post to connect one substrate to another substrate, where each substrate can be a chip, wafer, printed circuit board, packaging substrate, or the like, thus The above connection can be chip-to-chip, chip-to-chip, chip-to-chip, chip or chip to printed circuit board or packaging substrate, etc. While any pillar size may be used with these embodiments, it has been found that these embodiments are particularly useful for smaller pillar size...
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Abstract
A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.
Description
technical field [0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having pillar structures with non-planar surfaces. Background technique [0002] In recent years, technological changes in electronic devices and semiconductor packaging have impacted the entire semiconductor industry. The introduction of surface mount technology (surface mount technology; SMT) and ball grid array (ball grid array; BGA) packaging technology has become a key step in the high-yield assembly of various integrated circuit (IC) devices, and at the same time reduces the size of the printed circuit board. spacing between pads. Traditionally, the structure of packaged integrated circuits has used thin gold wires between the metal pads on the chip and the electrodes extending to the outside of the molded resin package as the basic interconnection. Dual Inline Package (DIP) or Quad Flat Package (Quad Flat Package) is the basic structure of ...
Claims
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IPC IPC(8): H01L23/485H01L21/60H01L23/488H01L21/48
CPCH01L2224/13169H01L2224/05681H01L2224/03912H01L2224/13018H01L2924/01082H01L2224/13022H01L24/03H01L2224/13076H01L2224/05666H01L24/05H01L2924/01019H01L2924/01327H01L2224/13144H01L2924/01029H01L2924/00013H01L2224/13147H01L2924/01022H01L2924/19041H01L2224/03452H01L24/11H01L2924/014H01L2924/01013H01L2224/05572H01L2924/01072H01L2224/0345H01L2924/01047H01L2924/01079H01L2224/13155H01L24/13H01L2224/13139H01L2924/14H01L2224/05647H01L2924/01005H01L2924/01033H01L2924/01006H01L2224/13084H01L2924/01074H01L2924/01078H01L2924/01073H01L2224/16507H01L2224/13111H01L2924/00014H01L2924/0002H01L2224/0401H01L2924/15788H01L2924/181H01L2224/0361H01L2224/13016H01L2224/1308H01L2224/13099H01L2224/13599H01L2224/05599H01L2224/05099H01L2224/29099H01L2224/29599H01L2224/05552H01L2924/00
Inventor 郭庭豪陈承先萧景文
Owner TAIWAN SEMICON MFG CO LTD