Packaging structure for system level fan-out wafer

Abstract

The invention relates to a packaging structure for a system level fan-out wafer, and the packaging structure comprises a packaging material layer, a chip, a passive device, a metal re-wiring layer, a protective film layer, an under bump metal layer and metal solder balls, wherein the chip and the passive device are packaged and cured in the packaging material layer; the chip and the functional surface of the passive device are exposed on the surface of the packaging material layer; the metal re-wiring layer is formed on the surface of the packaging material layer and electrically connected with the chip and the functional surface of the passive device; the protective film layer is formed on the surface of the packaging material layer, and an opening for exposing the metal re-wiring layer is arranged on the protective film layer; the under bump metal layer which is connected with the metal re-wiring layer is formed in the opening; and the metal solder balls are formed on the under bump metal layer. The chip and the passive device in the packaging structure are integrated and then packaged together, thereby forming a packaging product with integral system function rather than the single chip function, having high degree of integration, further reducing resistance, inductance and other interference factors in the system, and better complying with the requirements of the trend of enabling the packaging of semiconductors to be light, thin, short and small.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a system-level fan-out wafer packaging structure. Background technique [0002] Wafer Level Packaging (WLP) technology is a technology that performs packaging and testing on the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is exactly the same as that of the bare chip. Wafer-level chip-scale packaging technology has completely subverted traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic Leadless Chip Carrier). Small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology has reached a high degree of miniaturization, and the cost of the chip is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is a technol...

AI Technical Summary

Problems solved by technology

[0004] The final product packaged and manufactured according to the above method has only a single chip function

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