Method for high-efficiency task scheduling of heterogeneous multi-core processor

A multi-core processor and task scheduling technology, applied in multi-programming devices, resource allocation, sustainable buildings, etc., can solve problems that affect the task scheduling performance of multi-core processors, the efficiency of task scheduling is not ideal, and the priority of key tasks is not high. , to achieve good application prospects, eliminate communication overhead, and reduce communication overhead

Inactive Publication Date: 2011-09-21
HARBIN ENG UNIV
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AI Technical Summary

Problems solved by technology

However, the task scheduling efficiency of heterogeneous multi-core processors is still not ideal, and there are problems such as excessive communication overhead, low priority of key tasks, and too many redundant tasks, which seriously affect the task scheduling performance of multi-core processors.

Method used

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  • Method for high-efficiency task scheduling of heterogeneous multi-core processor
  • Method for high-efficiency task scheduling of heterogeneous multi-core processor
  • Method for high-efficiency task scheduling of heterogeneous multi-core processor

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Embodiment Construction

[0018] Hereinafter, the present invention will be described in more detail with examples in conjunction with the accompanying drawings:

[0019] Combine figure 1 The invented efficient task scheduling method for heterogeneous multi-core processors includes the following modules:

[0020] 1. The clustering optimization processing module of the pre-task graph

[0021] Depth-first traverses all nodes in the DAG, and clusters and optimizes some special tasks with high communication overhead. By clustering the tasks whose communication overhead accounts for a large total task overhead, the execution time of the entire task is reduced, the entire application task graph is optimized, and a strong guarantee is provided for obtaining the subsequent efficient task scheduling results.

[0022] The clustering task must meet three conditions at the same time: (1) The current node has only one direct predecessor node; (2) The current node is the only direct successor node of its direct predecessor ...

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Abstract

The invention provides a method for high-efficiency task scheduling of a heterogeneous multi-core processor. The method comprises the following steps of: clustering certain special tasks which are large in communication overhead and easy to cluster in a task image to a precursor node of the tasks by adopting a linear task clustering method; starting from a topological structure of the whole task image, selecting parameters capable of comprehensively reflecting the importance of the task in the whole task image as priority weights; selecting a free critical path node to perform allocation first, and if multiple free critical path nodes exist, allocating the free critical path nodes in a sequence from high to low according to the node priority weights, and allocating all non-critical path free nodes in a sequence from high to low according to the priority weights; performing redundancy judgment, and deleting redundant tasks in a scheduling result; and performing adjustment according to the scheduling result after deleting the redundant tasks, and recalculating the earliest finish time of each task. According to the method, the efficiency of the task scheduling of the heterogeneous multi-core processor is improved, the power consumption of the processor is reduced, and the performance of the multi-core processor is promoted.

Description

Technical field [0001] The invention relates to a method for improving processor performance. Specifically, it is an efficient task scheduling method based on heterogeneous multi-core. Background technique [0002] With people's endless pursuit of high-performance microprocessors, in the past few decades, relying on traditional methods of increasing the processor clock frequency, the frequency of single-core processors has been greatly increased, and has now reached 4GHz. At the same time, due to the continuous improvement of processor frequency and the increase of chip integration, the power consumption and heat dissipation of single-core processors are becoming more and more serious. The traditional technology of developing processor parallelism through superscalar and super pipeline makes processing The design cost of the processor is getting higher and higher, and it is overwhelmed, and the performance of the single-core processor encounters a bottleneck. However, the ever-...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/46G06F9/50
CPCY02B60/142Y02B60/167Y02D10/00
Inventor 李静梅李静
Owner HARBIN ENG UNIV
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