Parallel five-bypass bin context-adaptive binary arithmetic coder-decoder

Abstract

The invention discloses a parallel five-bypass bin context-adaptive binary arithmetic coder-decoder, which comprises a three-bypass bin decoder coupled with a two-bypass bin decoder. The three-bypass bin decoder comprises a first input end used for receiving a bin stream, a second input end used for receiving a plurality of range values, a first output end used for outputting a first bypass bin, a second output end used for outputting a second bypass bin, a third output tend used for outputting a third bypass bin and a fourth output end used for outputting a shift bin stream. The two-bypass bin decoder comprises the first input end used for receiving the shift bin stream, the second input end used for receiving the plurality of range values, the first output end used for outputting a fourth bypass bin and the second output end used for outputting a fifth bypass bin.

Description

technical field [0001] The invention relates to a multi-bit full-text adaptive binary arithmetic coding decoder, in particular to a parallel five-bypass full-text adaptive binary arithmetic coding decoder. Background technique [0002] The full-text adaptive binary arithmetic coding (Context-adaptive Binary Arithmetic Coding, CABAC) decoding algorithm uses basic continuous operations to calculate the range, offset and look-up table for context variables. The data-dependent nature of full-text adaptive binary arithmetic coding and decoding results in 3 billion operations per second when processing high-definition images in real time, making full-text adaptive binary arithmetic coding and decoding difficult To achieve high-speed decoding. Basically, the full-text adaptive binary arithmetic coding bit decoder includes a decision bit decoder and a bypass bit decoder. Through experiments, it can be known that 80%-90% of all bits are encoded as decision bits, while the rest are c...

AI Technical Summary

Problems solved by technology

Although U.S. Patent No. 7,262,722 of Jahanghir et al. has disclosed a method for improving the performance of full-text adaptive binary arithmetic coding using a parallel architecture, the full-text adaptive binary arithmetic coding decoding algorithm is not like video decoding of other H.264 / AVC standards tool, it is not easy to improve the performance of full-text adaptive binary arithmetic coding using parallel architecture

Because the decoding of the full-text adaptive binary arithmetic coding uses sequential decoding, however, the continuous sequential decoding will make the full-text adaptive binary arithmetic coding decoding the main bottleneck of the H.264 / AVC standard

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