Method for improving error correction capacity and related memory device and controller of memory device

Abstract

The invention relates to a method for improving error correction capacity and a related memory device and a controller of the memory device. The method comprises the following steps of: respectively calculating a plurality of first parity check codes aiming at a plurality of lines of a data bit array; respectively calculating a plurality of second parity check codes aiming at a plurality of groups formed by a plurality of rows of the data bit array, wherein each of the groups comprises two or more of the rows, and the groups are not overlapped; and performing encoding / decoding corresponding to the first and second parity check codes. The invention also provides a related memory device and a controller of the memory device. In the invention, the error correction capacity of the controller of the memory device can be improved without increasing error correction code engine encoding / decoding digit, and the remaining storage space can be properly utilized by the realized error correction without causing waste. Therefore, the aim of giving consideration to operation efficiency and system resource use control and management can be fulfilled under the conditions of not increasing the chip area and related cost.

Description

technical field [0001] The present invention relates to the technical field of error correction of flash memory (Flash Memory) control chips, and more particularly, to a method that can improve a memory without increasing the number of encoding / decoding bits of an error correction code engine (Error Correction Code Engine, ECC Engine). A method of error correction capability of a controller of a device and associated memory device and controller thereof. Background technique [0002] In recent years, due to the continuous development of flash memory technology, various portable memory devices (eg, memory cards conforming to SD / MMC, CF, MS, and XD standards) are widely implemented in many applications. Therefore, the access control of the flash memory in these portable memory devices has become a very hot topic. [0003] For the commonly used NAND flash memory, it can be mainly divided into two types of flash memory: single level cell (Single Level Cell, SLC) and multiple le...

AI Technical Summary

Problems solved by technology

However, problems caused by the instability of multi-level cell flash memory have also emerged one by one

In view of these many problems, although related technologies provide some solutions, they are always unable to take into account the operational efficiency and system resource usage control

Therefore, no matter which solution is adopted, there will often be corresponding side effects

[0005] In particular, the error correction implemented according to related technologies usually does not use up all the storage space of the flash memory, and the remaining storage space cannot be used to store data, which is quite wasteful.

Please note that the typical reason for not using all the storage space of the flash memory in the related art is that once the number of encoding / decoding bits of the Error Correction Code Engine (ECC Engine) is increased, the cost of the Error Correction Code Engine will increase significantly. For example, increasing the number of encoding / decoding bits from 24 bits to 36 bits for 1K data will cause a large increase in the chip area of ​​the error correction code engine, which is about 1.5 times larger

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