Clock generation circuit and clock generation method

Abstract

The invention discloses a clock generation circuit and a clock generation method. The clock generation circuit comprises a phase detector, a first filter device, a charge pump, a second filter device and a controllable oscillator, wherein the phase detector is used for detecting a phase difference between a first clock and a second clock to generate a detection result; the first filter device is used for filtering the detection result; the charge pump is used for generating a control signal according to the filtered detection result; the second filter device is used for filtering the control signal; and the controllable oscillator is used for generating an output clock according to the filtered control signal, wherein the output clock is used for generating the second clock.

Description

technical field [0001] The present invention relates to a clock generating circuit and its related method, especially a phase-locked loop which can improve a ripple signal and its related method. Background technique [0002] Please refer to Figure 1A and Figure 1B . Figure 1A Shown is a schematic diagram of a traditional phase-locked loop circuit (Phase-locked Loop Circuit) 10, Figure 1B Shown is a timing diagram of various signals within the phase locked loop circuit 10 . The traditional PLL circuit 10 includes a Phase / Frequency Detector (Phase / Frequency Detector) 12, a charge pump 14, a low-communication wave device 16 and a voltage-controlled oscillator 18. Please refer to Figure 1A , which will not be described further here. Generally speaking, the conventional PLL circuit 10 uses the phase / frequency detector 12 to detect a phase difference between a reference clock S1' and a feedback clock S2', and uses a charge pump 14 to receive the first The phase signal Sd1...

AI Technical Summary

Problems solved by technology

Moreover, adjusting the current signal Sa' generated by the charge pump 14 into a pulse wave type does not bring significant benefits to the traditional phase-locked loop circuit 10, but may cause the control signal Scon' of a voltage-controlled oscillator 18 to appear Ripple (Ripple) signal (that is, the arrows at time points t1, t2...t4)

Images