Phase rotator and clock data recovery device

Abstract

The invention relates to the field of integrated circuit design, and discloses a phase rotator and a clock data recovery device, which only need to input one clock signal, which reduces the design difficulty of the phase rotator. The phase rotator provided by the present invention includes: MOS field effect transistors M1 to M8, a bias voltage selection module, first and second delay circuits, and controls the bias voltage selection module to output an N-bit control signal through control information, and the N-bit Each bit of the control signal is connected to a gate of M7, and an M-bit control signal is output through the second output terminal, and each bit of the M-bit control signal is connected to a gate of M8, so that the phase rotator can pass the control information Select the conduction number of M7 and M8 to realize phase rotation.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a phase rotator and a clock data recovery device. Background technique [0002] In the backplane SERDES (serial-to-parallel conversion circuit) application or some optical port SERDES applications, for the sake of reducing area and power consumption, the CDR (clock data recovery) in SERDES no longer adopts a double-ring structure, but uses Data recovery is achieved by means of a phase rotator. Compared with the CDR with a double-loop structure, the CDR with a phase rotator in SERDES has the following advantages: the TX side and the RX side can share a PLL (phase-locked loop), and only one clock slice clock segment can be used in SERDES to drive The multi-channel data slice data segment greatly reduces the power consumption of SERDES and reduces the area of ​​SERDES. [0003] Existing general-purpose phase rotators generally fall into the following two types: a phase rot...

AI Technical Summary

Problems solved by technology

The disadvantage of this structure is that it needs to input multi-phase clocks, and requires more SW (short for sum and weight) units, which increases the power consumption and area of ​​the phase rotator, and it is difficult to achieve strict matching of many SWs.

The disadvantage is that the phase rotator needs a PLL input quadrature clock, which will increase the area and power consumption of the phase rotator, and increase the design difficulty of the phase rotator

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