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Semiconductor device and manufacturing method thereof

一种半导体、器件的技术，应用在半导体器件及其制造领域，能够解决电阻增加、不能获得高速操作等问题，达到改善可靠性的效果

Active Publication Date: 2017-04-12
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the resistance of the gate electrode and the source / drain regions increases, causing a problem that high-speed operation cannot be obtained even when the field effect transistor is shrunk

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

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Embodiment Construction

[0058] Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. It should be noted that in all the drawings used to illustrate this embodiment, members having the same function are designated by the same reference numerals, and repeated description thereof is omitted. In addition, in the following embodiments, description of the same or similar components will not be repeated in principle unless particularly necessary.

[0059] will refer to figure 1 and FIG. 2 describe the semiconductor device of this embodiment. figure 1 is a cross-sectional view of a semiconductor device in which a MIS (Metal Insulator Semiconductor) type FET (Field Effect Transistor) (hereinafter abbreviated as MISFET) is formed over a semiconductor substrate 1 .

[0060] like figure 1 As shown, the main surface of the semiconductor substrate 1 has a first region and a second region separated by an isolation region 4 formed in the upper su...

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Abstract

The invention provides a semiconductor device and a manufacturing method thereof. A semiconductor device in which a metal silicide layer is formed by a salicide process is improved in reliability. A metal silicide layer is formed over the respective surfaces of the gate electrode, the n+ type semiconductor region, and the p+ type semiconductor region by a salicide process according to a local reaction method. In the first heat treatment at the time of forming the metal silicide layer, the heat treatment of the semiconductor wafer is performed using a heat conduction type annealing apparatus. In the second heat treatment, the heat treatment of the semiconductor wafer is performed using a microwave annealing apparatus, thereby lowering the temperature of the second heat treatment and preventing abnormal growth of the metal silicide layer. Therefore, junction leakage current in the metal silicide layer is reduced.

Description

[0001] Cross References to Related Applications [0002] The entire disclosure of Japanese Patent Application No. 2010-259022 filed on Nov. 19, 2010 including specification, drawings and abstract is hereby incorporated by reference. technical field [0003] The present invention relates to a semiconductor device and its manufacturing method, and more particularly, to a technique effective when applied to manufacturing a semiconductor element having a metal silicide layer. Background technique [0004] With the increase in the degree of integration of semiconductor devices, field effect transistors (MISFET: Metal Insulator Semiconductor Field Effect Transistor) have been scaled down according to scaling rules. However, the resistance of the gate electrode and the source / drain regions increases, causing a problem that high-speed operation cannot be obtained even when the field effect transistor is scaled down. In order to solve this problem, a Salicide (Self Aligned Silicide...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L29/43
CPCH01L21/28H01L29/43H01L21/28052H01L21/28518H01L21/324H01L21/67103H01L21/67115H01L21/6719H01L21/6875H01L21/823814H01L21/823835H01L29/665
Inventor 山口直
Owner RENESAS ELECTRONICS CORP