Optimization of static timing analysis of coupling interconnects

Abstract

The invention discloses an optimization method of static timing analysis of coupling interconnects, which mainly solves the defect that inductance of the coupling interconnects is not considered in the existing method. The method comprises the following implementation steps of: (1) recording process nodes; (2) reading interconnection information according to process node parameters, and storing the interconnection information in a Matlab software; (3) calculating a part value according to the interconnection information stored in the Matlab software; (4) calculating the part valve of an equivalent interconnect according to the previous part value; (5) calculating time delay of the coupling interconnects according to the calculated part value of the equivalent interconnect; (6) executing optimization of static timing analysis according to the interconnection time delay. In the optimization, the process of calculating the interconnection time delay contains the coupling effect of interconnection, so that the time delay calculation result is more accurate; and the method can be used for calculating the time delay of the process node data in the earlier stage of integrated circuit design, thereby improving the design efficiency of the integrated circuit.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and further relates to an optimization method for static timing analysis of coupled RLC interconnection lines in the field of microelectronic integrated circuits. The invention can be used in the early stage of the integrated circuit design project, considering the coupling situation, quickly and approximate calculation to obtain the delay of the coupling interconnection line and optimize the static timing analysis. Background technique [0002] With the rapid improvement of the integration and speed of integrated circuits, interconnection is an important factor affecting the performance of integrated circuit design in the process of deep submicron integrated circuit design. With the increase of the clock frequency of integrated circuits and the increase of the scale of interconnection lines of integrated circuits, the delay caused by coupling capacitance and coupling inductance effects ...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that although this method reduces the computational complexity to O(n 2 ), but the calculation process still involves a large amount of matrix budget, the calculation scale is relatively large, very complex, and the execution efficiency is low; and the patent uses the total capacitance and total inductance for calculation, without considering the coupling inductance and coupling capacitance, and the calculation results are not accurate. Can not adapt to the requirements of integrated circuit design under the new technology

Images