On-chip network mapping method based on ant-colony chaos genetic algorithm

A technology of chaotic genetics and network-on-a-chip, applied in the field of network-on-chip mapping based on ant colony chaotic genetic algorithm, can solve problems such as inability to meet the communication requirements between multi-cores

Inactive Publication Date: 2012-06-20
NANJING UNIV
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

With the further increase of the number of cores on a chip, traditional architectures, such as crossbar switches and hierarchical buses, cannot meet the communication requirements between multi-cores. For this reason, the Network-on-Chip (No

Method used

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  • On-chip network mapping method based on ant-colony chaos genetic algorithm
  • On-chip network mapping method based on ant-colony chaos genetic algorithm
  • On-chip network mapping method based on ant-colony chaos genetic algorithm

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Experimental program
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Effect test

Embodiment 1

[0079] To verify the invention, the algorithm is applied to the mapping problem of MPEG4 decoder. MPEG4 decoder can be decomposed into 12 tasks, such as image 3 As shown, and then they are handed over to 12 IP cores for execution respectively. The mapping problem at this time is how to place these 12 IP cores on a NoC with a scale of 3x4.

[0080] Before formally applying the present invention to solve this problem, we need to define the mathematical expression of the objective function cost.

[0081] First, the system energy consumption is defined as:

[0082] E ( C ) = Σ i = 1 N Σ j = 1 N w i , j × h ...

Embodiment 2

[0094] In order to fully reflect the advantages of the present invention, a series of random task graphs are generated, and the NoC is mapped and optimized with emphasis on different optimization objectives (λ=1, 0.5, 0), and then the mapping results are carried out with the standard ant colony algorithm compared. In this embodiment, the definition of the objective function still adopts the formula (19) in Embodiment 1. The end result is as Image 6 shown. Image 6 The comparison results of communication energy consumption and link load variance of each mapping scheme with standard ant colony algorithm are shown when λ=1, 0.5, 0. It can be seen from the figure that the present invention is obviously superior to the traditional ant colony algorithm. When λ=1, the cost of the mapping scheme is 11% lower than that of the reference scheme; when λ=0.5, the cost of the mapping scheme is 4% lower than that of the reference scheme; when λ=0, the cost of the mapping scheme is 1% low...

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Abstract

Disclosed is an on-chip network mapping method based on the ant-colony chaos genetic algorithm. The standard ant-colony algorithm is basically used and the genetic algorithm is introduced in the on-chip network mapping method, parameters about each ant are coded by real numbers, codes of the ants are utilized as chromosome in the genetic algorithm, and algorithm parameters of coded ants are adjusted by the genetic algorithm in each iteration. During running of the algorithm, recycled results of each iteration of the algorithm are monitored, if the fact that the algorithm is trapped in a local optimum solution is monitored, mutation probability of the genetic algorithm is increased by a method of introducing a chaos model, and further, the parameters of the ant-colony algorithm are changed by means of the genetic algorithm. By the aid of the on-chip network mapping method, capability of the anti-colony chaos genetic algorithm for searching the solution space can be improved effectively, and trapping in the local optimum solution is avoided. In addition, the on-chip network mapping method has excellent practical values and wide application prospect for solution of massive on-chip network mapping.

Description

technical field [0001] The invention relates to an on-chip network mapping method, specifically a mapping method that can effectively improve the search efficiency of the mapping algorithm in the solution space and avoid the algorithm from falling into a local optimal solution, and is an on-chip network mapping based on an ant colony chaotic genetic algorithm method. Background technique [0002] With the semiconductor process technology entering the nanometer stage and the continuous improvement of on-chip integration, the global connection delay has risen to several times the chip clock, and the traditional architecture has been unable to meet the System-on-a-Chip (SoC) communication. need. Although the performance of traditional single-core processor chips can be improved by further increasing the integration level, the overhead will be too large, and various related bottleneck problems will become increasingly difficult to solve. Therefore, the method of replacing a si...

Claims

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Application Information

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IPC IPC(8): G06F17/50G06N3/12
Inventor 潘红兵易伟何书专王佳文李丽
Owner NANJING UNIV
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