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A method for efficient utilization of rs error correction and detection algorithm in flash memory controller

A flash memory controller and error correction and detection technology, which is applied in the field of efficient utilization of RS error correction and detection algorithm, can solve the problems of high resource occupancy rate and low resource o Excellent error detection performance and extended service life

Active Publication Date: 2016-01-06
雷智数系统技术西安有限公司
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Problems solved by technology

[0003] The purpose of the present invention is to provide a method for efficiently utilizing the RS error correction and detection algorithm in the flash memory controller, which solves the defect of high resource occupancy of the error correction and detection module in the prior art, and its resource occupancy is low and does not affect data Transmission rate

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  • A method for efficient utilization of rs error correction and detection algorithm in flash memory controller

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[0034] The error correction and detection module of the present invention adopts the RS code on the GF(2^8) field, and each symbol is 8bit (1 byte), wherein the original data length is 128 bytes, and the check information length is 2 bytes, correcting 1 byte error; for 512 bytes of data, 8 bytes of check information will be generated to correct 4 byte errors.

[0035] Structurally, the RS error correction and detection module adopts a combination of parallel and serial, such as figure 1 As shown, the 32-bit data line is first divided into high 16 bits and low 16 bits, and sent to two RS modules respectively, then each RS error correction algorithm module only needs to complete the encoding and decoding calculation of the 16-bit data interface. For 16-bit wide data, it is first given to a 16-bit wide cache. When the data in the cache is valid, use a 2-fold clock to read the lower 8-bit data in the cache as the first clock. The first original data is sent to the RS error correc...

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Abstract

The invention relates to a method for efficiently utilizing a Reed-Solomon (RS) error detection and correction algorithm in a flash memory controller. The method comprises the following steps of: providing two RS error detection and correction algorithm modules, and finishing the parallel coding and decoding operation of 32-bit data interface data by double frequency-doubled clock time division multiplexing. A series-parallel combined time division multiplexing method is adopted for the RS error detection and correction algorithm modules, so that the occupancy rate of resources is reduced, the data transmission rate is not influenced, and the error detection and correction performance of RS codes is ensured; the error detection and correction performance is high, and the service life of a flash memory is prolonged; and the RS error detection and correction algorithm modules are serially connected, so that the pipeline operation of data is ensured.

Description

technical field [0001] The invention relates to an efficient utilization method of an RS error correction and detection algorithm, in particular to an efficient utilization method of an RS error correction and detection algorithm in a flash memory controller. Background technique [0002] In conventional flash memory controllers, ECC, BCH, and RS error correction and detection algorithms are usually used. Compared with BCH algorithm and RS algorithm, ECC algorithm is simpler to implement and occupies less resources, but its error correction capability is limited. For a 512-byte data, 3-byte verification information will be generated, which can only correct 1-bit errors and detect 2-bit errors. Therefore, if there are too many errors in the flash memory chip, the ECC algorithm will be unable to do what it wants. The error correction ability of the BCH algorithm is stronger than that of ECC, and it is good at dealing with random errors. However, BCH processes data bit by bit. ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/42
Inventor 刘升张伟
Owner 雷智数系统技术西安有限公司
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