Non-leaded package structure and manufacturing method thereof

Abstract

The invention provides a non-leaded package structure and a manufacturing method thereof. The manufacturing method comprises providing a metal base plate which has an upper surface and a lower surface opposite to each other. The upper surface and the lower surface of a metal base plate are patterned so as to form a plurality of first protruding parts and at least a second protruding part on the upper surface and to form a plurality of first recess patterns on the lower surface corresponding to the first protruding parts. A first solder layer is formed in each of the first recess patterns respectively. A chip is mounted on the second protruding part. A plurality of bonding wires are formed for electrically connecting the chip to the first protruding parts respectively. An encapsulant is formed on the upper surface of the metal base plate. A back etching process is performed on the lower surface of the metal base plate with the first solder layer serving as an etch mask to partially remove the metal base plate until the encapsulant is exposed and a lead group is defined, wherein the lead group comprises at least a die pad carrying the chip and a plurality of leads isolated to one another.

Description

technical field [0001] The present invention relates to a package structure without external leads, and in particular to a quad / dual flat non-leaded package (Quad / Dual Flat Non-leaded package, QFN / DFN package) with protruding leads structure and method of manufacture. Background technique [0002] Semiconductor packaging technology includes many packaging forms, among which the quad / two-square flat no-lead package belonging to the flat package series has a short signal transmission path and relatively fast signal transmission speed, so the four-square / two-square flat no-lead The pin package is suitable for high-frequency transmission (such as radio frequency band) chip package, and is one of the mainstream low pin count (low pin count) package types. [0003] In the process of QFNP, a plurality of chips are firstly arranged on a planar leadframe. Then, the chip is electrically connected to the lead frame by a plurality of wires. Finally, part of the lead frame, wires and ...

AI Technical Summary

Problems solved by technology

However, it is difficult for the lead frame used by the four-square / two-square flat no outer pin to achieve the number of pins other than a single row. Therefore, when users have higher and higher requirements for the pin density of the lead frame, how to use the package technology to form the required pin density is a problem to be solved

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