Sample preparation method for wafer-level back failure positioning in failure analysis
A technology of failure analysis and failure location, applied in the direction of semiconductor/solid-state device testing/measurement, etc., can solve the problems of wasting time, complicated use process, unusable testing of wafers, etc., to improve quality, ensure integrity, and realize backside The effect of failure positioning
Active Publication Date: 2012-08-15
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology
[0003] The purpose of the present invention is to provide a sample preparation method for wafer-level backside failure location in failure analysis, to solve the problem that traditional failure analysis sample preparation methods need to chop wafers, but the chopped wafers cannot be used for wafers Level testing, and the use process is complicated, but also a waste of time
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[0024] In the first embodiment of the present invention, please continue to refer to Figure 2a to Figure 2e shown. The wafer 1 mentioned above can be the whole or a part of a wafer sample.
[0025] In the second embodiment of the present invention, the adhesive tape 3 is insulating, stickable and removable, so that it can be pasted on the wafer 1 or removed.
[0026] In the third embodiment of the present invention, the conductive tape 4 is conductive and matched with the electric wire 6 . Commonly used conductive strips 4 include copper strips and aluminum strips.
[0027] In the fourth embodiment of the present invention, the above-mentioned electric wire 6 can be made of materials such as aluminum, gold or copper.
[0028] In the fifth embodiment of the present invention, the aforementioned target point 2 of the wafer 1 may be a mold or a test key.
[0029] In summary, using a sample preparation method for wafer-level backside failure location in failure analysis of th...
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The invention discloses a sample preparation method for wafer-level back failure positioning in failure analysis. The method is characterized by comprising the following steps of: providing a wafer; searching for a target point in front of the wafer; sticking an adhesive tape at the target point close to the wafer and on the back of the wafer; then sticking a conduction band on the adhesive tape; connecting an electric wire to the target point and the conduction band; and finally detecting by use of a probe on the conduction band on the back of the wafer. Through the sample preparation method for wafer-level back failure positioning in failure analysis, disclosed by the invention, a good back failure positioning result can be obtained without cutting the wafer, the cost of the failure analysis is effectively saved, and the quality is improved. Through the invention, the integrity of the wafer is effectively guaranteed, and the back failure positioning is realized.
Description
technical field [0001] The invention relates to a microelectronic sample preparation method, in particular to a sample preparation method for wafer-level backside failure location in failure analysis. Background technique [0002] Modern IC manufacturing processes, for example, increasing the level and density of interconnections between metals, have produced failure localization using conventional emission microscopy, and are more difficult on an IC manufacturing process basis. Therefore, failure localization by the size of the silicon behind the IC is a solution. figure 1 For a schematic illustration of the traditional sample preparation method, see figure 1 shown. The traditional failure analysis sample preparation method for backside failure location is to cut the whole wafer into small pieces, then install the small pieces of wafer 8 on the carrier 9, and paste the conductive tape 4 on the carrier 9, and finally Reconnection is then made via aluminum or copper wires ...
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Inventor 陈强
Owner SHANGHAI HUALI MICROELECTRONICS CORP