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Sample preparation method for wafer-level back failure positioning in failure analysis

A technology of failure analysis and failure location, applied in the direction of semiconductor/solid-state device testing/measurement, etc., can solve the problems of complicated use process, waste of time, and unusable testing of wafers, so as to improve quality, ensure integrity, and realize backside The effect of failure positioning

Active Publication Date: 2014-09-17
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a sample preparation method for wafer-level backside failure location in failure analysis, to solve the problem that traditional failure analysis sample preparation methods need to chop wafers, but the chopped wafers cannot be used for wafers Level testing, and the use process is complicated, but also a waste of time

Method used

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  • Sample preparation method for wafer-level back failure positioning in failure analysis
  • Sample preparation method for wafer-level back failure positioning in failure analysis
  • Sample preparation method for wafer-level back failure positioning in failure analysis

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Embodiment approach

[0024] In the first embodiment of the present invention, please continue to refer to Figure 2a to Figure 2e Shown. The aforementioned wafer 1 can be the whole or a part of a wafer sample.

[0025] In the second embodiment of the present invention, the adhesive tape 3 has insulating properties, as well as stickability and removability, which is convenient for sticking on the wafer 1 or removing it.

[0026] In the third embodiment of the present invention, the conductive tape 4 has conductivity and is matched with the wire 6. Commonly used conductive tape 4 includes copper tape and aluminum tape.

[0027] In the fourth embodiment of the present invention, the above-mentioned wire 6 may use materials such as aluminum, gold, or copper.

[0028] In the fifth embodiment of the present invention, the aforementioned target point 2 of the wafer 1 may be a mold or a test key.

[0029] In summary, using a sample preparation method for wafer-level backside failure location in failure analysis ...

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Abstract

The invention discloses a sample preparation method for wafer-level back failure positioning in failure analysis. The method is characterized by comprising the following steps of: providing a wafer; searching for a target point in front of the wafer; sticking an adhesive tape at the target point close to the wafer and on the back of the wafer; then sticking a conduction band on the adhesive tape; connecting an electric wire to the target point and the conduction band; and finally detecting by use of a probe on the conduction band on the back of the wafer. Through the sample preparation method for wafer-level back failure positioning in failure analysis, disclosed by the invention, a good back failure positioning result can be obtained without cutting the wafer, the cost of the failure analysis is effectively saved, and the quality is improved. Through the invention, the integrity of the wafer is effectively guaranteed, and the back failure positioning is realized.

Description

Technical field [0001] The invention relates to a microelectronic sample preparation method, in particular to a sample preparation method for wafer-level backside failure positioning in failure analysis. Background technique [0002] Modern IC manufacturing process, for example, to improve the level and density of interconnection between metals, through the use of conventional emission microscopes have produced failure location, and it is more difficult on the basis of IC manufacturing process. Therefore, it is a solution to locate failures by the size of silicon behind the IC. figure 1 For a schematic diagram of the traditional sample preparation method, please see figure 1 Shown. The traditional failure analysis sample preparation method for backside failure location is to cut the whole wafer into small pieces, then mount the small wafer 8 on the carrier 9, and paste the conductive tape 4 on the carrier 9, and finally Reconnect it through the aluminum or copper wire 6 and use ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
Inventor 陈强
Owner SHANGHAI HUALI MICROELECTRONICS CORP