Check node updating circuit and method of LDPC (low-density parity-check) decoder

A technology for checking nodes and updating circuits, applied in error detection coding using multi-bit parity bits, error correction/detection using block codes, data representation error detection/correction, etc. problems such as power consumption, excessive hardware resources, etc., to achieve the effect of saving quantity, less hardware resources, and benefiting performance

Inactive Publication Date: 2012-08-15
SOUTH CHINA UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Usually, the traditional check node update module circuit will use too many hardware resources, thus increasing the complexity of t

Method used

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  • Check node updating circuit and method of LDPC (low-density parity-check) decoder
  • Check node updating circuit and method of LDPC (low-density parity-check) decoder
  • Check node updating circuit and method of LDPC (low-density parity-check) decoder

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Embodiment

[0043] Such as figure 1 Shown is the flowchart of the check node updating circuit of a kind of LDPC decoder of the present invention:

[0044] A method for updating a check node of an LDPC decoder, comprising the steps of:

[0045] (1) Decompose the 15-bit wide check node rin of the check node information memory into six 6-bit wide information data, which are rin0, rin1, rin2, rin3, rin4, rin5, and the principle of decomposition is Restore the 15-bit wide check node rin that contains the last check node update information; for the check node rin, rin[5:0] represents the sign bits of rin5~rin0 in turn, and rin[8:6] represents The index of the minimum value in rin0~rin5, rin[11:9] represents the value of the second smallest value in rin0~rin5, and rin[14:12] represents the value of the minimum value in rin0~rin5.

[0046] (2) Six 6-bit wide information data are subtracted from six 6-bit wide information nodes in the information node memory to obtain six 6-bit wide output data,...

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Abstract

The invention discloses a check node updating circuit and method of an LDPC (low-density parity-check) decoder. The check node updating circuit comprises a decomposition circuit, a subtraction circuit, a sign bit and data bit decomposition circuit, a data evaluation circuit, a sign bit processing circuit and a merging circuit. The check node updating circuit disclosed by the invention is based on 1/2 code rate LDPC codes used in the China Mobile Multimedia Broadcasting standard, and the decoding method adopts a layered min-sum algorithm and is based on a minimum value and second smallest value calculation algorithm of a pointer. The check node updating circuit disclosed by the invention is low in implementation complexity and few in used hardware resources, and can be used for saving the number of comparators and preventing excess information from being generated.

Description

technical field [0001] The present invention relates to a low density parity check (LDPC) decoder used for data transmission error correction or error detection in a digital communication system, in particular to a check node update circuit and method of an LDPC decoder, the check node update circuit It is 1 / 2 code rate, based on the pointer-based algorithm for finding the minimum value and the second minimum value, which can save the number of comparators and will not generate redundant information, which is beneficial to the performance of the decoder. Background technique [0002] Channel coding is a very important part of the communication system, which ensures the reliability of the entire communication system. Nowadays, mobile communication tends to be more and more real-time and high-speed transmission. In this case, users pay more attention to data reliability. Therefore, the algorithm research and hardware implementation of channel coding with excellent performance ...

Claims

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Application Information

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IPC IPC(8): H03M13/11
Inventor 姜小波叶德盛
Owner SOUTH CHINA UNIV OF TECH
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