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Method for synchronously displaying signals in batch on spliced wall

A signal synchronization and splicing wall technology, applied in the field of splicing wall display, can solve problems such as blue screen, signal display window out of sync, blurred screen, etc.

Inactive Publication Date: 2012-10-03
GUANGDONG VTRON TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When switching from one batch signal display mode to another batch signal display mode, there will be a delay in configuring multiple signal window parameters in the large-screen splicing wall, which will lead to out-of-sync signal display windows, blurred screens, blue screens, etc.

Method used

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  • Method for synchronously displaying signals in batch on spliced wall
  • Method for synchronously displaying signals in batch on spliced wall

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Embodiment Construction

[0018] In the traditional technology, the FPGA logic processing unit of the splicing wall only has a first-level register, and the root cause of the asynchronous image display is that it takes a long time to write data to the register. The invention solves the problem of asynchronous display of batch signals on the mosaic wall from the perspective of reducing the writing time of register data. The present invention will be explained in detail below in conjunction with the accompanying drawings and embodiments.

[0019] The method for synchronously displaying batch signals of the mosaic wall in the present invention, such as figure 1 shown, including steps:

[0020] Step S1, configuring temporary registers, effective control registers and synchronization control registers in the FPGA logic processing unit of the splicing wall;

[0021] Step S2, the effective control register saves the configuration parameters of the current batch of signals;

[0022] Step S3, the temporary r...

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Abstract

The invention discloses a method for synchronously displaying signals in batch on a spliced wall. A FPGA (Field Programmable Gate Array) logic processing unit on the spliced wall is equipped with two levels of registers, namely a temporary register and an effective control register, wherein the effective control register is used for storing the configuration parameter of the current batch of signals, and the temporary register is used for storing the configuration parameter of the next batch of signals. Before signal switching, the data of the signals to be displayed is prestored in the temporary register, and after the prestoring operation, the data in the temporary register is latched to the effective control register through a synchronous control register so that the FPGA logic processing unit of the spliced wall perform the processing and display operations according to the data in the effective control register. By adoption of the prestoring mode, the time that the effective control register obtains data is greatly saved, the phenomenon of asynchronous image display in different signal windows is avoided, and the user experience is improved.

Description

technical field [0001] The invention relates to the technical field of splicing wall display, in particular to a method for synchronously displaying batch signals of a splicing wall. Background technique [0002] In order to meet the various needs of users, the signal sources of large-screen splicing walls are becoming more and more diverse. For the convenience of operation, the operation of displaying multiple signals at the same time is usually set to the batch signal display mode at the video wall control terminal. When switching from one batch signal display mode to another batch signal display mode, there will be a delay in configuring multiple signal window parameters in the large-screen splicing wall, which will lead to out-of-sync signal display windows, blurred screens, blue screens, etc. . Contents of the invention [0003] Based on the above situation, the present invention proposes a method for synchronously displaying batch signals on a video wall, so as to ...

Claims

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Application Information

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IPC IPC(8): G09G5/12
Inventor 胡军模伍健庭
Owner GUANGDONG VTRON TECH CO LTD
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