Package assembly having a semiconductor substrate

Abstract

Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and / or claimed.

Description

[0001] Cross References to Related Applications [0002] This disclosure claims priority to U.S. Patent Application No. 12 / 973,249, filed December 20, 2010, which in turn claims U.S. Provisional Patent Application No. 61 / 295,925, filed January 18, 2010, April 2010 U.S. Provisional Patent Application No. 61 / 328,556, filed May 27, U.S. Provisional Patent Application No. 61 / 333,542, filed May 11, 2010, U.S. Provisional Patent Application No. 61 / 347,156, filed May 21, 2010 , and U.S. Provisional Patent Application No. 60 / 350,852, filed June 2, 2010; the entire specification of these patent applications is adopted in its entirety for all purposes except for those sections (such as if any) that are inconsistent with this specification incorporated herein by reference. technical field [0003] Embodiments of the present disclosure relate to the field of integrated circuits, and more particularly to techniques, structures, and configurations of semiconductor substrates for packaging...

AI Technical Summary

Problems solved by technology

For example, stacked substrate techniques may not produce sufficiently small structural elements on the substrate to correspond to the finer pitches of interconnects or other signal routing structural elements formed on the die

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