Mixed crystal face double polycrystal BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device based on self-aligning process and manufacturing method thereof

A self-aligned process, mixed crystal plane technology, applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve problems such as limitation and low mobility of Si material carrier materials

Active Publication Date: 2012-10-17
陕西半导体先导技术中心有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Due to the low mobility of Si material carrier materials, the performance of integrated circuits manufactured using Si BiCMOS technology, especially the frequency performance, is greatly limited; for SiGe BiCMOS technology, although SiGe HBT is used for bipolar transistors, However, Si CMOS is still used for unipolar devices that restrict the improvement of the frequency characteristics of BiCMOS integrated circuits, so these limit the further improvement of the performance of BiCMOS integrated circuits

Method used

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  • Mixed crystal face double polycrystal BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device based on self-aligning process and manufacturing method thereof

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0127] Embodiment 1: Preparation of 22nm mixed crystal plane double polycrystalline strained BiCMOS integrated device and circuit based on self-alignment process, the specific steps are as follows:

[0128] Step 1, SOI substrate material preparation.

[0129] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0130] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;

[0131] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

[0132] (1d) SiO on th...

Embodiment 2

[0194] Embodiment 2: Preparation of 30nm mixed crystal plane double polycrystalline strained BiCMOS integrated device and circuit based on self-alignment process, the specific steps are as follows:

[0195] Step 1, SOI substrate material preparation.

[0196] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0197] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;

[0198] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen...

Embodiment 3

[0261] Embodiment 3: Preparation of 45nm mixed crystal plane double polycrystalline strained BiCMOS integrated device and circuit based on self-alignment process, the specific steps are as follows:

[0262] Step 1, SOI substrate material preparation.

[0263] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0264] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si wafer with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;

[0265] (1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;

[0266] (1d) SiO on the surface of ...

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Abstract

The invention discloses a mixed crystal face double polycrystal BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device based on a self-aligning process and a manufacturing method of the mixed crystal face double polycrystal BiCMOS integrated device. The method comprises the following steps of: growing an N-type Si extensional layer as the bipolar device collector region on an SOI (Silicon on Insulator) substrate; manufacturing deep trench isolation; subsequently manufacturing base polycrystal, a base region and an emitter region sequentially so as to form a SiGe HBT (Heterojunction Vipolar Transistor) device; etching a deep trench at an area of an NMOS (N-Channel Metal Oxide Semiconductor) device; selectively growing a strain Si extensional layer of which the crystal face is (100); manufacturing a Si channel NMOS device; at an active area of a PMOS (P-Channel Metal Oxide Semiconductor) device, selectively growing a strain SiGe extensional layer of which the crystal face is (110); manufacturing a SiGe channel PMOS device; and forming the mixed crystal face double polycrystal BiCMOS integrated device and a circuit of the mixed crystal face double polycrystal BiCMOS integrated device. The characteristics that the hole mobility of a tensile strain Si material is higher than that of a body Si material and the mobility of the compressive strain SiGe material is higher than that of the body Si material are fully utilized; and moreover, the performance-enhanced mixed crystal face double polycrystal BiCMOS integrated device and the circuit of the performance-enhanced mixed crystal face double polycrystal BiCMOS integrated device are manufactured based on the SOI substrate.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a mixed crystal plane double-polycrystalline strained BiCMOS integrated device and a preparation method based on a self-alignment process. Background technique [0002] In the contemporary era of highly developed information technology, microelectronic technology represented by integrated circuits is the key to information technology. As the fastest-growing, most influential and most widely used technology in human history, integrated circuits have become an important symbol to measure a country's scientific and technological level, comprehensive national strength and national defense strength. [0003] "Moore's Law", which has had a huge impact on the development of the microelectronics industry, states that the number of transistors on an integrated circuit chip doubles approximately every 18 months, and the performance also doubles. For m...

Claims

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Application Information

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Patent Type & AuthorityApplications(China)
IPC IPC(8): H01L27/06H01L21/8249
Inventor胡辉勇张鹤鸣周春宇宋建军李妤晨宣荣喜舒斌郝跃
Owner陕西半导体先导技术中心有限公司