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Method for forming dielectric layer

A dielectric layer and dielectric layer surface technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as changes in the capacitance value of ultra-low-k dielectric layers, serious problems in the stability and reliability of semiconductor devices, etc. , to achieve the effect of preventing k value drift and large changes in capacitance, ensuring stability and reliability

Active Publication Date: 2012-11-28
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] In the prior art, when metal wiring or conductive plugs are formed in the ultra-low-k dielectric layer, the dielectric constant k value of the ultra-low-k dielectric layer will drift, resulting in a change in the capacitance value of the ultra-low-k dielectric layer (such as ultra-low-k dielectric layer The capacitance of the dielectric layer is 40% higher than that of the low-k dielectric layer), causing serious problems in the stability and reliability of semiconductor devices

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  • Method for forming dielectric layer

Examples

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no. 1 example

[0031] Figure 6 to Figure 11 It is a schematic diagram of the first embodiment of forming a semiconductor device including an ultra-low-k dielectric layer according to the present invention (taking the formation of a metal wiring layer as an example). Such as Image 6 As shown, a semiconductor substrate 100 is provided. Structures such as transistors, capacitors, and metal wiring layers are usually formed on the semiconductor substrate 100 through previous processes;

[0032] In this embodiment, the dielectric layer 200 is an ultra-low-k dielectric layer with a dielectric constant of 2.2 to 2.59, and the ultra-low-k dielectric layer is a porous material; the material of the ultra-low-k dielectric layer is SiOCH, and the SiOCH The spacing between atoms is relatively sparse; the method of forming an ultra-low-k dielectric layer is chemical vapor deposition.

[0033] Such as Figure 7 As shown, an anti-reflection layer 300 is formed on the surface of the dielectric layer 200 ...

no. 2 example

[0045] Figure 12 to Figure 18 It is a schematic diagram of a second embodiment of forming a semiconductor device including an ultra-low-k dielectric layer according to the present invention (taking the formation of a conductive plug of a dual damascene structure as an example). Such as Figure 12 As shown, a semiconductor substrate 1000 is provided. Structures such as transistors, capacitors, and metal wiring layers are usually formed on the semiconductor substrate 1000 through previous processes;

[0046] In this embodiment, the dielectric layer 2000 is an ultra-low-k dielectric layer with a dielectric constant of 2.2 to 2.59, and the ultra-low-k dielectric layer is a porous material; the material of the ultra-low-k dielectric layer is SiOCH, and the SiOCH The spacing between atoms is relatively sparse; the method of forming an ultra-low-k dielectric layer is chemical vapor deposition.

[0047] Such as Figure 13 As shown, a first anti-reflection layer 3000 is formed on t...

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Abstract

The invention discloses a method for forming a dielectric layer. The method comprises the following steps of: supplying a semiconductor substrate; forming the dielectric layer on the semiconductor substrate; etching or flattening the dielectric layer, and absorbing water in the dielectric layer through etching or flattening; and treating the surface of the dielectric layer by using far infrared. By the method, the influence of the water on the dielectric constant of an ultralow-k dielectric layer is avoided; drift of a k value and great change of capacitance of the ultralow-k dielectric layer are effectively prevented; and the stability and the reliability of a semiconductor device are guaranteed.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for forming a dielectric layer. Background technique [0002] At present, in the back-end process of semiconductor manufacturing, in order to connect various components to form an integrated circuit, metal materials with relatively high conductivity such as copper are usually used for wiring, that is, metal wiring. Whereas, conductive plugs are usually used for connection between metal wirings. The structures used to connect the active regions of semiconductor devices to other integrated circuits are typically conductive plugs. Existing conductive plugs are formed through a via process or a dual damascene process. [0003] In the existing process of forming copper wiring or conductive plugs, trenches or via holes are formed by etching the dielectric layer, and then conductive substances are filled in the trenches or via holes. However, when the feature size rea...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L21/3105
Inventor 周鸣
Owner SEMICON MFG INT (SHANGHAI) CORP