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Formation method of dielectric layer

A dielectric layer and dielectric constant technology, used in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as changes in the capacitance value of ultra-low-k dielectric layers, and prevent k-value drift and large changes in capacitance. Guarantee stability and reliability, enhance the effect of bonding force

Active Publication Date: 2015-11-25
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] In the prior art, when metal wiring or conductive plugs are formed in the ultra-low-k dielectric layer, the dielectric constant k value of the ultra-low-k dielectric layer will drift (k value becomes larger), resulting in a change in the capacitance value of the ultra-low-k dielectric layer changes, causing serious problems in the stability and reliability of semiconductor devices

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Examples

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no. 1 example

[0033] Figure 6 to Figure 11 It is a schematic diagram of the first embodiment of forming a semiconductor device including an ultra-low-k dielectric layer according to the present invention (taking the formation of a metal wiring layer as an example). Such as Figure 6 As shown, a semiconductor substrate 100 is provided. Structures such as transistors, capacitors, and metal wiring layers are usually formed on the semiconductor substrate 100 through previous processes; a dielectric layer 200 is deposited on the semiconductor substrate 100 .

[0034] In this embodiment, the dielectric layer 200 is an ultra-low-k dielectric layer with a dielectric constant of 2.2 to 2.59; the material of the ultra-low-k dielectric layer is SiCOH, and the interatomic spacing of the SiCOH is relatively sparse; forming an ultra-low The method of the k-dielectric layer is chemical vapor deposition.

[0035] Such as Figure 7 As shown, the first treatment 300 is performed on the dielectric layer 2...

no. 2 example

[0043] Figure 11 to Figure 16 It is a schematic diagram of a second embodiment of forming a semiconductor device including an ultra-low-k dielectric layer according to the present invention (taking the formation of a conductive plug of a dual damascene structure as an example). Such as Figure 12 As shown, a semiconductor substrate 1000 is provided, and structures such as transistors, capacitors, and metal wiring layers are usually formed on the semiconductor substrate 1000 through previous processes; a dielectric layer 2000 is deposited on the semiconductor substrate 1000 .

[0044] In this embodiment, the dielectric layer 2000 is an ultra-low-k dielectric layer with a dielectric constant of 2.2 to 2.59; the material of the ultra-low-k dielectric layer is SiCOH, and the interatomic spacing of SiCOH is relatively sparse; forming an ultra-low The method of the k-dielectric layer is chemical vapor deposition.

[0045] Such as Figure 12 As shown, the first treatment 3000 is ...

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Abstract

The invention relates to a method for forming a dielectric layer, which comprises the following steps: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; carrying out primary treatment on the dielectric layer to enhance the binding force of silicon-oxygen linkage on the surface of the dielectric layer; etching the dielectric layer until the semiconductor substrate is exposed, thereby forming a trench or through hole; fully filling a metal layer into the trench or through hole; and carrying out secondary treatment on the dielectric layer to lower the dielectric constant of the dielectric layer. The invention effectively prevents the k value drift of the ultralow-k dielectric layer and the great variation of the capacitance, and ensures the stability and reliability of the semiconductor device.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for forming a dielectric layer. Background technique [0002] At present, in the back-end process of semiconductor manufacturing, in order to connect various components to form an integrated circuit, metal materials with relatively high conductivity such as copper are usually used for wiring, that is, metal wiring. Whereas, conductive plugs are usually used for connection between metal wirings. The structures used to connect the active regions of semiconductor devices to other integrated circuits are typically conductive plugs. Existing conductive plugs are formed through a via process or a dual damascene process. [0003] In the existing process of forming copper wiring or conductive plugs, trenches or via holes are formed by etching the dielectric layer, and then conductive substances are filled in the trenches or via holes. However, when the feature size rea...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/268H01L21/768
Inventor 邓浩张彬
Owner SEMICON MFG INT (SHANGHAI) CORP