Implementation method for quickly reading peak in GPU (graphics processing unit)
An implementation method and vertex technology, applied in the direction of processor architecture/configuration, etc., can solve problems such as small Burst, inability to fully utilize DDR bandwidth, command transmission speed not keeping up with drawing speed, etc.
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[0007] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.
[0008] Such as figure 1 As shown, an implementation structure for fast reading vertices in GPU. The CPU configures the initial storage address of the primitive vertex data through the PCI bus (the primitive data is stored in a fixed format, the format of the vertices of the line segment is X, Y, Z, W, R, G, B, A, and the format of the vertices of the triangle is X, Y, Z, W, R, G, B, A, S, T, 0, 0), and then the CPU sends commands to the command analysis module through the PCI bus, and the command analysis module obtains the command data by reading the asynchronous FIFO, if it is legal The command decodes each component in the command word and sends it to the primitive management module; the primitive management module sends a request to the DDR controller with a larger BurstLength through the read vertex data module according to the ...
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