Tiled rendering based implementation method for multi-pipeline rendering in GPU (graphics processing unit)
A technology of block rendering and implementation method, applied in the direction of image memory management, etc., can solve the problem of not being able to maximize the operating efficiency of the GPU for block rendering, and achieve the effect of convenient implementation, simple implementation, and simple logic.
Active Publication Date: 2014-03-12
CHANGSHA JINGJIA MICROELECTRONICS
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Problems solved by technology
At present, in the GPU based on block rendering, because only one pipeline is used for rendering, the operating efficiency of the block rendering GPU cannot be maximized.
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[0007] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. Such as figure 1 As shown, it is an implementation structure of multi-pipeline rendering in GPU based on block rendering realized by the present invention. It includes drawing command analysis, 2D drawing module - to complete functions such as 2D screen clearing and dot matrix characters, primitive management - to complete the acquisition of primitive vertices and attributes, geometric transformation / lighting, clipping, screen coordinate transformation, primitive block, M rasterization pipelines, M Z / Stencil test pipelines, M texture mapping pipelines, M fusion pipelines, graphics display and other modules. The software sends drawing commands and parameter configuration commands to the GPU hardware through the PCI bus. After receiving the commands, the GPU enters the command parsing module, reads the vertices of the primitives from the...
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The invention discloses a tiled rendering based implementation method for multi-pipeline rendering in a GPU (graphics processing unit), which comprises the following steps of: analyzing a drawing command; taking a 2D drawing module to finish functions of 2D clear screen, dot-matrix and the like; carrying out graphics primitive management to finish the acquisition of a graphics primitive peak and the attribute. The tiled rendering based implementation method for multi-pipeline rendering in the GPU is carried out by a geometric transformation / illumination module, a cutting module, a screen coordinate transformation module, a graphics primitive partitioning module, an M-strip rasterization pipeline module, an M-strip Z / Stencil test pipeline module, an M-strip texture mapping pipeline module, an M-strip fusion pipeline module, a graphics display module and the like. According to the implementation structure, a purpose of performance acceleration of tiled rendering is realized by resource copying.
Description
technical field [0001] The present invention mainly relates to the field of GPU design based on block rendering, in particular to the realization of multi-pipeline rendering in GPU based on block rendering. Background technique [0002] The block rendering technology is proposed to alleviate the inefficiency caused by frequent memory access in traditional GPUs. Traditional GPU adopts fixed pipeline technology. Rendering a primitive needs to go through multiple processes of reading and writing memory such as Z test, texture, Alpha test, and fusion. A pixel may not need to be actually written into the frame memory after multiple memory accesses. The performance loss caused by this is very large. In order to alleviate this problem, block rendering technology was proposed. This technology is to divide the drawing area into several blocks of equal size. After the primitives are divided into blocks, they are drawn in the order of the blocks when drawing. It ensures that when d...
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IPC IPC(8): G06T1/60
Inventor 饶先宏
Owner CHANGSHA JINGJIA MICROELECTRONICS