Strain SiGe vertical CMOS (complementary metal-oxide-semiconductor transistor) integrated device and preparation method thereof

An integrated device and device technology, which is applied in the field of strained SiGe vertical CMOS integrated devices and fabrication, can solve the problems of inability to further reduce device size, threshold voltage drift, oxide layer breakdown, etc. The effect of improving flexibility

Inactive Publication Date: 2012-12-19
XIDIAN UNIV
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] As the feature size of the device enters the sub-50nm stage, many difficulties are encountered in the research process of the strained Si and SiGe CMOS planar structures: short channel effects, hot carrier effects, etc. make the device size unable to be further reduced; gate oxidation The thinning of the layer thickness leads to the breakdown of the oxide layer, and the tunneling current causes the threshold voltage to drift; the polysilicon depletion effect and the resistance of the polysilicon have an increasing influence on the threshold voltage, etc., all of which make the device and circuit performance unable to continue according to Moore. As the law of development continues to develop, it becomes more important to study devices with new structures.

Method used

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  • Strain SiGe vertical CMOS (complementary metal-oxide-semiconductor transistor) integrated device and preparation method thereof
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  • Strain SiGe vertical CMOS (complementary metal-oxide-semiconductor transistor) integrated device and preparation method thereof

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Effect test

Embodiment 1

[0051] Embodiment 1: The vertical structure strained SiGe CMOS integrated device and the circuit that the preparation conduction channel is 45nm, concrete steps are as follows:

[0052] Step 1, epitaxial material preparation, such as figure 2 shown.

[0053] (1a) Select the doping concentration as 1×10 15 cm -3 P-type Si substrate sheet 1;

[0054] (1b) Using chemical vapor deposition (CVD), grow an N-type Si epitaxial layer 2 with a thickness of 1.0 μm on the substrate at 600°C, with a doping concentration of 5×10 19 cm -3 , as the NMOS drain region;

[0055] (1c) Using the method of chemical vapor deposition (CVD), grow an N-type strained SiGe layer 3 with a thickness of 5 nm on the substrate at 600 °C, with a doping concentration of 5×10 18 cm -3 , the Ge composition is 10%, as the first N-type lightly doped source-drain structure (N-LDD) layer of NMOS;

[0056] (1d) Using chemical vapor deposition (CVD), at 600°C, grow a p-type strained SiGe layer 4 with a thickne...

Embodiment 2

[0107] Embodiment 2: The vertical structure strained SiGe CMOS integrated device and the circuit of preparing the conduction channel to be 30nm, concrete steps are as follows:

[0108] Step 1, epitaxial material preparation, such as figure 2 shown.

[0109] (1a) Select the doping concentration to be 5×10 15 cm -3 P-type Si substrate sheet 1;

[0110] (1b) Using chemical vapor deposition (CVD), grow an N-type Si epitaxial layer 2 with a thickness of 0.8 μm on the substrate at 700°C, with a doping concentration of 8×10 19 cm -3 , as the NMOS drain region;

[0111] (1c) Using chemical vapor deposition (CVD), grow an N-type strained SiGe layer 3 with a thickness of 4 nm on the substrate at 700 ° C, with a doping concentration of 3×10 18 cm -3 , the Ge composition is 10%, as the first N-type lightly doped source-drain structure (N-LDD) layer of NMOS;

[0112] (1d) Using chemical vapor deposition (CVD), grow a P-type strained SiGe layer 4 with a thickness of 30 nm on the su...

Embodiment 3

[0163] Embodiment 3: The vertical structure strained SiGe CMOS integrated device and the circuit of preparing the conduction channel to be 22nm, concrete steps are as follows:

[0164] Step 1, epitaxial material preparation, such as figure 2 shown.

[0165] (1a) Select the doping concentration as 1×10 16 cm -3 P-type Si substrate sheet 1;

[0166] (1b) Using chemical vapor deposition (CVD), grow an N-type Si epitaxial layer 2 with a thickness of 0.5 μm on the substrate at 750°C, with a doping concentration of 1×10 20 cm -3 , as the NMOS drain region;

[0167] (1c) Using chemical vapor deposition (CVD), grow an N-type strained SiGe layer 3 with a thickness of 3nm on the substrate at 750°C, with a doping concentration of 1×10 18 cm -3 , the Ge composition is 10%, as the first N-type lightly doped source-drain structure (N-LDD) layer of NMOS;

[0168](1d) Using chemical vapor deposition (CVD), grow a p-type strained SiGe layer 4 with a thickness of 22nm on the substrate ...

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Abstract

The invention discloses a strain SiGe vertical CMOS (complementary metal-oxide-semiconductor transistor) integrated device and a preparation method of the integrated device. The preparation method comprises the following steps of: continuously forming an N type Si epitaxial layer, an N type strain SiGe layer, a P type strain SiGe layer, an N type strain SiGe layer, an N type Si layer and an N type Si layer, an N type strain SiGe layer and an N type Si cap layer on a substrate NMOS (n-channel metal oxide semiconductor) active region and a substrate PMOS (p-channel metal oxide semiconductor) active region respectively at 600-780DEG C, isolating from one another, and respectively preparing a drain electrode, a grid electrode and a source region in the NMOS active region, so that the NMOS can be prepared; then, depositing SiO2 and Poly-Si in the PMOS active region, preparing a virtual grid electrode, depositing a medium layer to form a grid-side wall, and injecting by a self-aligning technology to form a PMOS source and a PMOS drain; and etching the virtual grid, and depositing SiON and W-TiN to from a grid medium and a composite metal grid respectively, so that the PMOS can be prepared, and the strain SiGe vertical CMOS integrated device and circuit can be formed. The characteristic that the vertical electronic mobility and the horizontal hole mobility of the strain SiGe material are higher than the relaxation Si is abundantly used, so that the strain SiGe CMOS integrated device and circuit with enhanced performance can be prepared under a low-temperature technology.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a strained SiGe vertical CMOS integrated device and a preparation method. Background technique [0002] Semiconductor integrated circuits are the foundation of the electronics industry, and people's huge demand for the electronics industry has prompted the rapid development of this field. In the past few decades, the rapid development of the electronics industry has had a huge impact on social development and national economy. At present, the electronics industry has become the largest industry in the world, occupying a large share in the global market, and its output value has exceeded 1 trillion US dollars. [0003] Si CMOS integrated circuits have the advantages of low power consumption, high integration, low noise and high reliability, and occupy a dominant position in the semiconductor integrated circuit industry. However, with the fur...

Claims

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Application Information

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Patent Type & AuthorityApplications(China)
IPC IPC(8): H01L27/092H01L21/8238H01L29/423H01L21/28
Inventor宋建军胡辉勇王斌张鹤鸣宣荣喜舒斌周春宇郝跃
OwnerXIDIAN UNIV