Multi-version code stream storage circuit architecture for configuration memory dedicated for FPGA (Field Programmable Gate Array)

Abstract

The invention relates to a multi-version code stream storage circuit architecture for a configuration memory dedicated for an FPGA (Field Programmable Gate Array). The multi-version code stream storage circuit architecture comprises a version selecting register 201, a version identification register group 202, XNOR logic 203, a data storage block array 204 and a multi-channel selector 205. According to the multi-version code stream storage circuit architecture, a data storage block array which can only store design code streams of one version in the traditional architecture is replaced with the data storage block array which can store the design code streams of multiple versions, and the selection of the code stream version can be carried out in a manner that a port is selected by using an external version or a control bit is selected by using an internal programmable version. With the adoption of the multi-version code stream storage circuit architecture for the configuration memory dedicated for the FPGA, disclosed by the invention, a single design code stream can be stored in one data storage block, and a design code stream with larger capacity can be stored by spanning multiple data storage blocks and even can be stored by spanning multiple configuration memories which are cascaded; and the configuration memory dedicated for the FPGA, which adopts the circuit architecture, supports online system multi-version code stream storage, so that the flexibility of FPGA-oriented configuration applications is greatly improved.

Description

technical field [0001] The invention relates to an FPGA-specific configuration memory multi-version code stream storage circuit architecture, which belongs to the technical field of integrated circuits. Background technique [0002] figure 1 It is a schematic diagram of a circuit interface for configuring a Field Programmable Gate Array (FPGA, Field Programmable Gate Array) by cascading multiple configuration memories. Here, in order to illustrate the configuration principle of the FPGA100 device and the cascadable characteristics of the configuration memory, only the interface signals related to the configuration and cascading characteristics are marked out, mainly including: control enable signal CE, control enable output signal CEO and FPGA configuration port 105; FPGA configuration port 105 mainly includes: configuration completion signal DONE, control bus 110, address bus 111 and data bus 112. [0003] For the configuration of the FPGA100 device, it is necessary to co...

AI Technical Summary

Problems solved by technology

[0005] The problem solved by the technology of the present invention is: to overcome the deficiencies of the prior art, provide a FPGA-specific configuration memory multi-version code stream storage circuit architecture, and solve the problem that the traditional FPGA-specific configuration memory can only store one version of the design code stream

Images