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Semiconductor device and method for making epitaxial layer

An epitaxial layer, semiconductor technology

Active Publication Date: 2017-11-07
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to reduce the manufacturing process variability caused by the micro-loading effect, semiconductor manufacturing processes such as selective epitaxial growth manufacturing processes can be carried out in corresponding regions according to the device pattern density. However, this method will increase production costs and time

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  • Semiconductor device and method for making epitaxial layer
  • Semiconductor device and method for making epitaxial layer
  • Semiconductor device and method for making epitaxial layer

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Embodiment Construction

[0029] In order to enable those who are familiar with the technical field of the present invention to further understand the present invention, the preferred embodiments of the present invention are listed below, together with the accompanying drawings, to describe in detail the composition of the present invention and the desired effects .

[0030] Please refer to Figure 1 to Figure 6 . Figure 1 to Figure 6 A schematic diagram of a method for fabricating an epitaxial layer according to a first preferred embodiment of the present invention is shown. Such as figure 1 As shown, a semiconductor substrate 10 including at least one groove 12 is provided. The semiconductor substrate 10 may have multiple regions (not shown) defined thereon, and each region has its own pattern density. To simplify the description, it is now taken as an example to form a transistor in a region with any device density. The semiconductor substrate 10 may include, for example, a substrate made of ga...

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Abstract

The invention discloses a semiconductor device and a method for making an epitaxial layer. The semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate has at least one iso region (or open region) and at least one dense region (dense region). A plurality of transistors are respectively arranged in the wide sparse region and the dense region, and each transistor includes at least one source / drain region, wherein the source / drain region each includes a first epitaxial layer having a bottom thickness and a side thickness, And the bottom thickness of the first epitaxial layer is substantially greater than or equal to the side thickness of the first epitaxial layer.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor device with an epitaxial layer and a manufacturing method thereof. Background technique [0002] With the development of semiconductors toward miniaturization, the dimensions of the gate, source, and drain of the transistor are also continuously reduced along with the reduction of the feature size. However, due to the limitations of the physical properties of the material, the reduction in the size of the gate, source, and drain will reduce the amount of carriers that determine the magnitude of the current in the transistor element, thereby affecting the performance of the transistor. Therefore, increasing the mobility of carriers to increase the speed of MOS transistors has become a major topic in the field of semiconductor technology. [0003] In currently known techniques, a selective epitaxial growth (SEG) process may be used to for...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/20H01L21/336H01L21/8234
Inventor 廖晋毅宣腾竣简金城
Owner UNITED MICROELECTRONICS CORP