Control circuit of DRAM (dynamic random access memory) column selection signal and access memory comprising same

Abstract

The invention belongs to the technical field of a DRAM (dynamic random access memory) and relates to a control circuit of a DARM column selection signal. The control circuit comprises a column selection signal generation circuit, a redundancy unit corresponding to a memory unit of the DARM and a redundant word line drive module, wherein the column selection signal generation circuit generates a column selection signal when the amplification read-out voltage of the redundancy unit is matched with a preset voltage threshold. The DARM comprises a memory array and a read path of the memory unit in the memory array, and is characterized in that the memory array also comprises the redundancy unit. The DARM also comprises the control circuit of the column selection signal. The DARM can increase the speed of read operation while guaranteeing the reliability of reading.

Description

technical field [0001] The invention belongs to the technical field of DRAM (Dynamic Random Access Memory, dynamic random access memory), relates to a control circuit of a column selection signal of a DRAM, in particular to a control circuit of a column selection signal including a redundant unit. Background technique [0002] DRAM has been widely used in electronic products such as computers, and its technology development cycle is relatively long and relatively mature. However, since DRAM is a memory that stores information based on charge, its read operation is relatively slow. As the requirements for the speed of the DRAM are getting higher and higher, the current main method is to increase the reading speed by continuously scaling down the DRAM. [0003] Generally, a DRAM includes a storage array and peripheral circuits (for controlling operations such as reading, writing, and refreshing). The storage array is also composed of a plurality of storage cells arranged in r...

AI Technical Summary

Problems solved by technology

figure 1 The shown DRAM column gating control method mainly has the following disadvantages: if YL is activated too early, the voltage on the bit line may be rapidly pulled down by the large capacitor on the IO line, so low that it cannot be re-amplified by SA, resulting in read mistake

Therefore, in the existing technology, the delay required in the worst case is usually adopted, that is, YL is activated later, but this brings additional read delay, which affects the read speed

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